diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala index fd265858..97bc39b6 100644 --- a/src/main/scala/groundtest/TestHarness.scala +++ b/src/main/scala/groundtest/TestHarness.scala @@ -12,7 +12,7 @@ class TestHarness(q: Parameters) extends Module { } implicit val p = q - val dut = Module(LazyModule(new GroundTestTop(new GroundTestCoreplex()(_))).module) + val dut = Module(LazyModule(new GroundTestTop).module) io.success := dut.io.success if (dut.io.mem_axi4.nonEmpty) { diff --git a/src/main/scala/groundtest/Top.scala b/src/main/scala/groundtest/Top.scala index 613bb39a..088d16f1 100644 --- a/src/main/scala/groundtest/Top.scala +++ b/src/main/scala/groundtest/Top.scala @@ -6,20 +6,25 @@ import diplomacy._ import coreplex._ import rocketchip._ -class GroundTestTop[+C <: GroundTestCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex) - with DirectConnection +class GroundTestTop(implicit p: Parameters) extends BaseTop with PeripheryMasterAXI4Mem with PeripheryTestRAM { override lazy val module = new GroundTestTopModule(this, () => new GroundTestTopBundle(this)) + + val coreplex = LazyModule(new GroundTestCoreplex) + + socBus.node := coreplex.mmio + coreplex.mmioInt := intBus.intnode + (mem zip coreplex.mem) foreach { case (m, c) => m := c } } -class GroundTestTopBundle[+L <: GroundTestTop[GroundTestCoreplex]](_outer: L) extends BaseTopBundle(_outer) +class GroundTestTopBundle[+L <: GroundTestTop](_outer: L) extends BaseTopBundle(_outer) with PeripheryMasterAXI4MemBundle with PeripheryTestRAMBundle { val success = Bool(OUTPUT) } -class GroundTestTopModule[+L <: GroundTestTop[GroundTestCoreplex], +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) +class GroundTestTopModule[+L <: GroundTestTop, +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) with PeripheryMasterAXI4MemModule with PeripheryTestRAMModule { io.success := outer.coreplex.module.io.success diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 76055561..5f2810c7 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -11,21 +11,19 @@ import uncore.tilelink2._ import uncore.devices._ import util._ import rocket._ -import coreplex._ /** Enable or disable monitoring of Diplomatic buses */ case object TLEmitMonitors extends Field[Boolean] -abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule { - val coreplex = LazyModule(_coreplex(p)) +abstract class BareTop(implicit val p: Parameters) extends LazyModule { TopModule.contents = Some(this) } -abstract class BareTopBundle[+L <: BareTop[BaseCoreplex]](_outer: L) extends Bundle { +abstract class BareTopBundle[+L <: BareTop](_outer: L) extends Bundle { val outer = _outer } -abstract class BareTopModule[+L <: BareTop[BaseCoreplex], +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) { +abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) { val outer = _outer val io = _io () } @@ -45,8 +43,6 @@ trait TopNetwork extends HasPeripheryParameters { TLWidthWidget(socBusConfig.beatBytes)( TLAtomicAutomata(arithmetic = peripheryBusArithmetic)( socBus.node)) - - var coreplexMem = Seq[TLOutwardNode]() } trait TopNetworkBundle extends HasPeripheryParameters { @@ -61,22 +57,13 @@ trait TopNetworkModule extends HasPeripheryParameters { } /** Base Top with no Periphery */ -class BaseTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BareTop(_coreplex) +class BaseTop(implicit p: Parameters) extends BareTop with TopNetwork { override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this)) } -class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](_outer: L) extends BareTopBundle(_outer) +class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer) with TopNetworkBundle -class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io) +class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io) with TopNetworkModule - -trait DirectConnection extends TopNetwork { - val coreplex: BaseCoreplex - - socBus.node := coreplex.mmio - coreplex.mmioInt := intBus.intnode - - coreplexMem = coreplex.mem -} diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala index 00cafe31..c0ec3d3c 100644 --- a/src/main/scala/rocketchip/ExampleTop.scala +++ b/src/main/scala/rocketchip/ExampleTop.scala @@ -5,56 +5,45 @@ package rocketchip import Chisel._ import config._ import junctions._ -import coreplex._ import rocketchip._ -/** Example Top with Periphery */ -class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex) - with DirectConnection +/** Example Top with Periphery (w/o coreplex) */ +abstract class ExampleTop(implicit p: Parameters) extends BaseTop with PeripheryExtInterrupts with PeripheryMasterAXI4Mem with PeripheryMasterAXI4MMIO { override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this)) } -class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer) +class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer) with PeripheryExtInterruptsBundle with PeripheryMasterAXI4MemBundle with PeripheryMasterAXI4MMIOBundle -class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) +class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) with PeripheryExtInterruptsModule with PeripheryMasterAXI4MemModule with PeripheryMasterAXI4MMIOModule -class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex) +class ExampleRocketTop(implicit p: Parameters) extends ExampleTop with PeripheryBootROM with PeripheryDTM with PeripheryCounter - with HardwiredResetVector { + with HardwiredResetVector + with RocketPlexMaster { override lazy val module = new ExampleRocketTopModule(this, () => new ExampleRocketTopBundle(this)) } -class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer) +class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer) with PeripheryBootROMBundle with PeripheryDTMBundle with PeripheryCounterBundle with HardwiredResetVectorBundle + with RocketPlexMasterBundle -class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) +class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) with PeripheryBootROMModule with PeripheryDTMModule with PeripheryCounterModule with HardwiredResetVectorModule - -/** Example Top with TestRAM */ -class ExampleTopWithTestRAM[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex) - with PeripheryTestRAM { - override lazy val module = new ExampleTopWithTestRAMModule(this, () => new ExampleTopWithTestRAMBundle(this)) -} - -class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](_outer: L) extends ExampleTopBundle(_outer) - with PeripheryTestRAMBundle - -class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) - with PeripheryTestRAMModule + with RocketPlexMasterModule diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 3cc38035..40b202cc 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -71,16 +71,17 @@ trait PeripheryExtInterruptsModule { ///// trait PeripheryMasterAXI4Mem { - this: BaseTop[BaseCoreplex] with TopNetwork => + this: TopNetwork => + val module: PeripheryMasterAXI4MemModule private val config = p(ExtMem) - private val channels = coreplexMem.size + private val channels = p(BankedL2Config).nMemoryChannels - val mem_axi4 = coreplexMem.zipWithIndex.map { case (node, i) => + val mem_axi4 = Seq.tabulate(channels) { i => val c_size = config.size/channels val c_base = config.base + c_size*i - val axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters( + AXI4BlindOutputNode(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( address = List(AddressSet(c_base, c_size-1)), regionType = RegionType.UNCACHED, // cacheable @@ -89,14 +90,12 @@ trait PeripheryMasterAXI4Mem { supportsRead = TransferSizes(1, 256), interleavedId = Some(0))), // slave does not interleave read responses beatBytes = config.beatBytes)) + } - axi4 := - // AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff - TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite - TLWidthWidget(coreplex.l1tol2_beatBytes)( // convert width before attaching to the l1tol2 - node)) - - axi4 + val mem = mem_axi4.map { node => + val foo = LazyModule(new TLToAXI4(config.idBits)) + node := foo.node + foo.node } } diff --git a/src/main/scala/rocketchip/RocketPlexMaster.scala b/src/main/scala/rocketchip/RocketPlexMaster.scala new file mode 100644 index 00000000..9cbe64ef --- /dev/null +++ b/src/main/scala/rocketchip/RocketPlexMaster.scala @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +package rocketchip + +import Chisel._ +import config._ +import diplomacy._ +import uncore.tilelink2._ +import uncore.devices._ +import util._ +import coreplex._ + +trait RocketPlexMaster extends TopNetwork { + val module: RocketPlexMasterModule + val mem: Seq[TLInwardNode] + + val coreplex = LazyModule(new DefaultCoreplex) + + socBus.node := coreplex.mmio + coreplex.mmioInt := intBus.intnode + (mem zip coreplex.mem) foreach { case (m, c) => m := c } +} + +trait RocketPlexMasterBundle extends TopNetworkBundle { + val outer: RocketPlexMaster +} + +trait RocketPlexMasterModule extends TopNetworkModule { + val outer: RocketPlexMaster + val io: RocketPlexMasterBundle +} diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala index 092a290b..465183f9 100644 --- a/src/main/scala/rocketchip/TestHarness.scala +++ b/src/main/scala/rocketchip/TestHarness.scala @@ -14,7 +14,7 @@ class TestHarness(q: Parameters) extends Module { val success = Bool(OUTPUT) } implicit val p = q - val dut = Module(LazyModule(new ExampleRocketTop(new DefaultCoreplex()(_))).module) + val dut = Module(LazyModule(new ExampleRocketTop).module) for (int <- dut.io.interrupts(0)) int := Bool(false)