riscv/rocket-chip
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rocketchip: cut coreplex from rocketchip

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This commit is contained in:
Wesley W. Terpstra
2016-11-22 15:01:45 -08:00
parent c80ee06472
commit a140b07009
7 changed files with 69 additions and 58 deletions
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2
src/main/scala/groundtest/TestHarness.scala
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@ -12,7 +12,7 @@ class TestHarness(q: Parameters) extends Module {
}
implicit val p = q
val dut = Module(LazyModule(new GroundTestTop(new GroundTestCoreplex()(_))).module)
val dut = Module(LazyModule(new GroundTestTop).module)
io.success := dut.io.success
if (dut.io.mem_axi4.nonEmpty) {

13
src/main/scala/groundtest/Top.scala
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@ -6,20 +6,25 @@ import diplomacy._
import coreplex._
import rocketchip._
class GroundTestTop[+C <: GroundTestCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
with DirectConnection
class GroundTestTop(implicit p: Parameters) extends BaseTop
with PeripheryMasterAXI4Mem
with PeripheryTestRAM {
override lazy val module = new GroundTestTopModule(this, () => new GroundTestTopBundle(this))
val coreplex = LazyModule(new GroundTestCoreplex)
socBus.node := coreplex.mmio
coreplex.mmioInt := intBus.intnode
(mem zip coreplex.mem) foreach { case (m, c) => m := c }
}
class GroundTestTopBundle[+L <: GroundTestTop[GroundTestCoreplex]](_outer: L) extends BaseTopBundle(_outer)
class GroundTestTopBundle[+L <: GroundTestTop](_outer: L) extends BaseTopBundle(_outer)
with PeripheryMasterAXI4MemBundle
with PeripheryTestRAMBundle {
val success = Bool(OUTPUT)
}
class GroundTestTopModule[+L <: GroundTestTop[GroundTestCoreplex], +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
class GroundTestTopModule[+L <: GroundTestTop, +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryMasterAXI4MemModule
with PeripheryTestRAMModule {
io.success := outer.coreplex.module.io.success