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Change MIF_DATA_BITS back to 64

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It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
This commit is contained in:
Palmer Dabbelt
2016-02-27 11:41:28 -08:00
parent 9ea8c4e781
commit a0f3189c74
2 changed files with 11 additions and 5 deletions
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2
src/main/scala/Configs.scala
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@@ -93,7 +93,7 @@ class DefaultConfig extends Config (
// Bits added by NASTI interconnect // Bits added by NASTI interconnect
max(log2Up(site(MaxBanksPerMemoryChannel)), max(log2Up(site(MaxBanksPerMemoryChannel)),
(if (site(UseDma)) 3 else 2))) (if (site(UseDma)) 3 else 2)))
case MIFDataBits => Dump("MIF_DATA_BITS", 128) case MIFDataBits => Dump("MIF_DATA_BITS", 64)
case MIFAddrBits => Dump("MIF_ADDR_BITS", case MIFAddrBits => Dump("MIF_ADDR_BITS",
site(PAddrBits) - site(CacheBlockOffsetBits)) site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits) case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)

14
vsrc/backup_mem.v
View File

@@ -54,7 +54,7 @@ module BackupMemory
output reg [`MIF_TAG_BITS-1:0] mem_resp_tag output reg [`MIF_TAG_BITS-1:0] mem_resp_tag
); );
localparam DATA_CYCLES = 4; localparam DATA_CYCLES = 8;
localparam DEPTH = 2*1024*1024; localparam DEPTH = 2*1024*1024;
reg [`ceilLog2(DATA_CYCLES)-1:0] cnt; reg [`ceilLog2(DATA_CYCLES)-1:0] cnt;
@@ -62,7 +62,7 @@ module BackupMemory
reg state_busy, state_rw; reg state_busy, state_rw;
reg [`MIF_ADDR_BITS-1:0] addr; reg [`MIF_ADDR_BITS-1:0] addr;
reg [`MIF_DATA_BITS-1:0] ram [DEPTH-1:0]; reg [127:0] ram [DEPTH-1:0];
wire [`ceilLog2(DEPTH)-1:0] ram_addr = state_busy ? {addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt} wire [`ceilLog2(DEPTH)-1:0] ram_addr = state_busy ? {addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt}
: {mem_req_addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt}; : {mem_req_addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt};
wire do_read = mem_req_valid && mem_req_ready && !mem_req_rw || state_busy && !state_rw; wire do_read = mem_req_valid && mem_req_ready && !mem_req_rw || state_busy && !state_rw;
@@ -97,9 +97,15 @@ module BackupMemory
cnt <= cnt + 1'b1; cnt <= cnt + 1'b1;
if (do_write) if (do_write)
ram[ram_addr] <= mem_req_data_bits; if (ram_addr[0] == 1'b0)
ram[ram_addr/2][63:0] <= mem_req_data_bits;
else
ram[ram_addr/2][127:64] <= mem_req_data_bits;
else else
mem_resp_data <= ram[ram_addr]; if (ram_addr[0] == 1'b0)
mem_resp_data <= ram[ram_addr/2][63:0];
else
mem_resp_data <= ram[ram_addr/2][127:64];
if (reset) if (reset)
mem_resp_valid <= 1'b0; mem_resp_valid <= 1'b0;