From a0f3189c7452760c7dadb0d7fd1866a3311beef4 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Sat, 27 Feb 2016 11:41:28 -0800 Subject: [PATCH] Change MIF_DATA_BITS back to 64 It turns out the Chisel C++ backend can't emit correct initialization code for a 128 bit wide NastiROM. Rather than trying to fix Chisel, I'm just going to hack up the backup memory port Verilog harness a bit more to make it work. Note that the backup memory port Verilog already couldn't take arbitrary parameters for MIF_*, so it's not like we're losing any flexibility here. --- src/main/scala/Configs.scala | 2 +- vsrc/backup_mem.v | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 8a16cc44..5022a6d6 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -93,7 +93,7 @@ class DefaultConfig extends Config ( // Bits added by NASTI interconnect max(log2Up(site(MaxBanksPerMemoryChannel)), (if (site(UseDma)) 3 else 2))) - case MIFDataBits => Dump("MIF_DATA_BITS", 128) + case MIFDataBits => Dump("MIF_DATA_BITS", 64) case MIFAddrBits => Dump("MIF_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits)) case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits) diff --git a/vsrc/backup_mem.v b/vsrc/backup_mem.v index 584f2db1..2d8ae383 100644 --- a/vsrc/backup_mem.v +++ b/vsrc/backup_mem.v @@ -54,7 +54,7 @@ module BackupMemory output reg [`MIF_TAG_BITS-1:0] mem_resp_tag ); - localparam DATA_CYCLES = 4; + localparam DATA_CYCLES = 8; localparam DEPTH = 2*1024*1024; reg [`ceilLog2(DATA_CYCLES)-1:0] cnt; @@ -62,7 +62,7 @@ module BackupMemory reg state_busy, state_rw; reg [`MIF_ADDR_BITS-1:0] addr; - reg [`MIF_DATA_BITS-1:0] ram [DEPTH-1:0]; + reg [127:0] ram [DEPTH-1:0]; wire [`ceilLog2(DEPTH)-1:0] ram_addr = state_busy ? {addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt} : {mem_req_addr[`ceilLog2(DEPTH/DATA_CYCLES)-1:0], cnt}; wire do_read = mem_req_valid && mem_req_ready && !mem_req_rw || state_busy && !state_rw; @@ -97,9 +97,15 @@ module BackupMemory cnt <= cnt + 1'b1; if (do_write) - ram[ram_addr] <= mem_req_data_bits; + if (ram_addr[0] == 1'b0) + ram[ram_addr/2][63:0] <= mem_req_data_bits; + else + ram[ram_addr/2][127:64] <= mem_req_data_bits; else - mem_resp_data <= ram[ram_addr]; + if (ram_addr[0] == 1'b0) + mem_resp_data <= ram[ram_addr/2][63:0]; + else + mem_resp_data <= ram[ram_addr/2][127:64]; if (reset) mem_resp_valid <= 1'b0;