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Change MIF_DATA_BITS back to 64

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It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
This commit is contained in:
Palmer Dabbelt
2016-02-27 11:41:28 -08:00
parent 9ea8c4e781
commit a0f3189c74
2 changed files with 11 additions and 5 deletions
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2
src/main/scala/Configs.scala
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@@ -93,7 +93,7 @@ class DefaultConfig extends Config (
// Bits added by NASTI interconnect
max(log2Up(site(MaxBanksPerMemoryChannel)),
(if (site(UseDma)) 3 else 2)))
case MIFDataBits => Dump("MIF_DATA_BITS", 128)
case MIFDataBits => Dump("MIF_DATA_BITS", 64)
case MIFAddrBits => Dump("MIF_ADDR_BITS",
site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)