riscv/rocket-chip
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change write/read port ordering for vlsi_mem_gen script

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Yunsup Lee 2013-01-29 21:32:42 -08:00
parent 66eb3720a4
commit a0bd0adeb2
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/util.scala
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@ -98,11 +98,11 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Component
val ram_out = Reg{Bits(width = data.getWidth)} val ram_out = Reg{Bits(width = data.getWidth)}
val ram_out_valid = Reg{Bool()} val ram_out_valid = Reg{Bool()}
ram_out_valid := Bool(false) ram_out_valid := Bool(false)
when (do_enq) { ram(enq_ptr) := io.enq.bits.toBits }
when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) { when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) {
ram_out_valid := Bool(true) ram_out_valid := Bool(true)
ram_out := ram(Mux(io.deq.valid, deq_ptr + UFix(1), deq_ptr)) ram_out := ram(Mux(io.deq.valid, deq_ptr + UFix(1), deq_ptr))
} }
when (do_enq) { ram(enq_ptr) := io.enq.bits.toBits }
io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid) io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid)
io.enq.ready := !full io.enq.ready := !full