riscv/rocket-chip
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tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps

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This commit is contained in:
Henry Cook 2013-04-10 13:53:27 -07:00
parent d7982bf27f
commit a01cdf95fd
3 changed files with 8 additions and 5 deletions
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2
riscv-rocket

@ -1 +1 @@
Subproject commit 31a4ad984cffb3c441e4b30a4c9060743f3295a8
Subproject commit d05e03fc57c1041e91c907e0d5600af810151c3c

9
src/main/scala/RocketChip.scala
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@ -211,11 +211,14 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
//reflection to automatically create enough networks for any given
//bundle containing LogicalNetworkIOs
val tl = new TileLinkType
val payloadBitsForEachPhysicalNetwork = tl.getClass.getMethods.filter( x =>
classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)).map(
val tileLinkDirectionalFIFOs = tl.getClass.getMethods.filter( x =>
classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType))
val payloadBitsForEachPhysicalNetwork = tileLinkDirectionalFIFOs.map(
_.invoke(tl).asInstanceOf[DirectionalFIFOIO[LogicalNetworkIO[Data]]].bits.payload)
val lockCountForEachPhysicalNetwork = tileLinkDirectionalFIFOs.map( x =>
if(classOf[ClientSourcedDataIO[Data]].isAssignableFrom(x.getReturnType)) REFILL_CYCLES else 1)
implicit val pconf = new PhysicalNetworkConfiguration(conf.nEndpoints, conf.idBits)//same config for all networks
val physicalNetworks: Seq[BasicCrossbar[Data]] = payloadBitsForEachPhysicalNetwork.map(d => (new BasicCrossbar){d.clone})
val physicalNetworks: Seq[BasicCrossbar[Data]] = lockCountForEachPhysicalNetwork zip payloadBitsForEachPhysicalNetwork map { case (c,d) => (new BasicCrossbar(c)){d.clone} }
//Use reflection to get the subset of each node's TileLink
//corresponding to each direction of dataflow and connect each sub-bundle

2
uncore

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Subproject commit c3ecc5388f7ba80c4600a551f8a81fd54bab0629
Subproject commit e39b29bac3889f43fa666bdd72d86b17d439b9ca