From a01cdf95fde87c177183b46748288a62c49ab8a8 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 10 Apr 2013 13:53:27 -0700 Subject: [PATCH] tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps --- riscv-rocket | 2 +- src/main/scala/RocketChip.scala | 9 ++++++--- uncore | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/riscv-rocket b/riscv-rocket index 31a4ad98..d05e03fc 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit 31a4ad984cffb3c441e4b30a4c9060743f3295a8 +Subproject commit d05e03fc57c1041e91c907e0d5600af810151c3c diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 405daad8..f641f346 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -211,11 +211,14 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit //reflection to automatically create enough networks for any given //bundle containing LogicalNetworkIOs val tl = new TileLinkType - val payloadBitsForEachPhysicalNetwork = tl.getClass.getMethods.filter( x => - classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)).map( + val tileLinkDirectionalFIFOs = tl.getClass.getMethods.filter( x => + classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)) + val payloadBitsForEachPhysicalNetwork = tileLinkDirectionalFIFOs.map( _.invoke(tl).asInstanceOf[DirectionalFIFOIO[LogicalNetworkIO[Data]]].bits.payload) + val lockCountForEachPhysicalNetwork = tileLinkDirectionalFIFOs.map( x => + if(classOf[ClientSourcedDataIO[Data]].isAssignableFrom(x.getReturnType)) REFILL_CYCLES else 1) implicit val pconf = new PhysicalNetworkConfiguration(conf.nEndpoints, conf.idBits)//same config for all networks - val physicalNetworks: Seq[BasicCrossbar[Data]] = payloadBitsForEachPhysicalNetwork.map(d => (new BasicCrossbar){d.clone}) + val physicalNetworks: Seq[BasicCrossbar[Data]] = lockCountForEachPhysicalNetwork zip payloadBitsForEachPhysicalNetwork map { case (c,d) => (new BasicCrossbar(c)){d.clone} } //Use reflection to get the subset of each node's TileLink //corresponding to each direction of dataflow and connect each sub-bundle diff --git a/uncore b/uncore index c3ecc538..e39b29ba 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit c3ecc5388f7ba80c4600a551f8a81fd54bab0629 +Subproject commit e39b29bac3889f43fa666bdd72d86b17d439b9ca