riscv/rocket-chip
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get rid of unused external mmio port

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This commit is contained in:
Howard Mao 2016-02-10 21:49:02 -08:00
parent 4b95374f0c
commit 9fb2216548
2 changed files with 5 additions and 15 deletions
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11
src/main/scala/Configs.scala
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@ -221,15 +221,14 @@ class DefaultConfig extends Config (
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64) case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true case UseBackupMemoryPort => true
case MMIOBase => Dump("MEM_SIZE", BigInt(1 << 30)) // 1 GB case MMIOBase => Dump("MEM_SIZE", BigInt(1L << 30)) // 1 GB
case ExternalIOStart => 2 * site(MMIOBase)
case DeviceTree => makeDeviceTree() case DeviceTree => makeDeviceTree()
case GlobalAddrMap => { case GlobalAddrMap => {
val extraSize = site(ExternalIOStart) - site(MMIOBase)
AddrMap( AddrMap(
AddrMapEntry("conf", None, MemSubmap(extraSize / 2, genCsrAddrMap)), AddrMapEntry("conf", None,
AddrMapEntry("devices", None, MemSubmap(extraSize / 2, site(GlobalDeviceSet).getAddrMap)), MemSubmap(BigInt(1L << 30), genCsrAddrMap)),
AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW))) AddrMapEntry("devices", None,
MemSubmap(BigInt(1L << 31), site(GlobalDeviceSet).getAddrMap)))
} }
case GlobalDeviceSet => { case GlobalDeviceSet => {
val devset = new DeviceSet val devset = new DeviceSet

9
src/main/scala/RocketChip.scala
View File

@ -27,8 +27,6 @@ case object UseBackupMemoryPort extends Field[Boolean]
case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent] case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
/** Function for building some kind of tile connected to a reset signal */ /** Function for building some kind of tile connected to a reset signal */
case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]] case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
/** Start address of the "io" region in the memory map */
case object ExternalIOStart extends Field[BigInt]
/** Enable DMA engine */ /** Enable DMA engine */
case object UseDma extends Field[Boolean] case object UseDma extends Field[Boolean]
@ -124,10 +122,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
outer.ar.bits.cache := UInt("b0011") outer.ar.bits.cache := UInt("b0011")
outer.aw.bits.cache := UInt("b0011") outer.aw.bits.cache := UInt("b0011")
} }
// tie off the mmio port
val errslave = Module(new NastiErrorSlave)
errslave.io <> uncore.io.mmio
} }
/** Wrapper around everything that isn't a Tile. /** Wrapper around everything that isn't a Tile.
@ -179,7 +173,6 @@ class Uncore(implicit val p: Parameters) extends Module
// Wire the htif to the memory port(s) and host interface // Wire the htif to the memory port(s) and host interface
io.host.debug_stats_csr := htif.io.host.debug_stats_csr io.host.debug_stats_csr := htif.io.host.debug_stats_csr
io.mem <> outmemsys.io.mem io.mem <> outmemsys.io.mem
io.mmio <> outmemsys.io.mmio
if(p(UseBackupMemoryPort)) { if(p(UseBackupMemoryPort)) {
outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
@ -204,7 +197,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
val csr = Vec(nTiles, new SmiIO(xLen, csrAddrBits)) val csr = Vec(nTiles, new SmiIO(xLen, csrAddrBits))
val scr = new SmiIO(xLen, scrAddrBits) val scr = new SmiIO(xLen, scrAddrBits)
val mmio = new NastiIO
val deviceTree = new NastiIO val deviceTree = new NastiIO
} }
@ -307,7 +299,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size) lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
} }
io.mmio <> mmio_ic.io.slaves(addrHashMap("io").port)
io.deviceTree <> mmio_ic.io.slaves(addrHashMap("conf:devicetree").port) io.deviceTree <> mmio_ic.io.slaves(addrHashMap("conf:devicetree").port)
val mem_channels = mem_ic.io.slaves val mem_channels = mem_ic.io.slaves