From 9fb2216548fafc14e9e759ee14a36b3d1e683af6 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 10 Feb 2016 21:49:02 -0800
Subject: [PATCH] get rid of unused external mmio port

---
 src/main/scala/Configs.scala    | 11 +++++------
 src/main/scala/RocketChip.scala |  9 ---------
 2 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index a0e18ab4..a0b66f30 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -221,15 +221,14 @@ class DefaultConfig extends Config (
       case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
       case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
       case UseBackupMemoryPort => true
-      case MMIOBase => Dump("MEM_SIZE", BigInt(1 << 30)) // 1 GB
-      case ExternalIOStart => 2 * site(MMIOBase)
+      case MMIOBase => Dump("MEM_SIZE", BigInt(1L << 30)) // 1 GB
       case DeviceTree => makeDeviceTree()
       case GlobalAddrMap => {
-        val extraSize = site(ExternalIOStart) - site(MMIOBase)
         AddrMap(
-          AddrMapEntry("conf", None, MemSubmap(extraSize / 2, genCsrAddrMap)),
-          AddrMapEntry("devices", None, MemSubmap(extraSize / 2, site(GlobalDeviceSet).getAddrMap)),
-          AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
+          AddrMapEntry("conf", None,
+            MemSubmap(BigInt(1L << 30), genCsrAddrMap)),
+          AddrMapEntry("devices", None,
+            MemSubmap(BigInt(1L << 31), site(GlobalDeviceSet).getAddrMap)))
       }
       case GlobalDeviceSet => {
         val devset = new DeviceSet
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 60a7f9e9..3e1efeaf 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -27,8 +27,6 @@ case object UseBackupMemoryPort extends Field[Boolean]
 case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
 /** Function for building some kind of tile connected to a reset signal */
 case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
-/** Start address of the "io" region in the memory map */
-case object ExternalIOStart extends Field[BigInt]
 /** Enable DMA engine */
 case object UseDma extends Field[Boolean]
 
@@ -124,10 +122,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
     outer.ar.bits.cache := UInt("b0011")
     outer.aw.bits.cache := UInt("b0011")
   }
-
-  // tie off the mmio port
-  val errslave = Module(new NastiErrorSlave)
-  errslave.io <> uncore.io.mmio
 }
 
 /** Wrapper around everything that isn't a Tile.
@@ -179,7 +173,6 @@ class Uncore(implicit val p: Parameters) extends Module
   // Wire the htif to the memory port(s) and host interface
   io.host.debug_stats_csr := htif.io.host.debug_stats_csr
   io.mem <> outmemsys.io.mem
-  io.mmio <> outmemsys.io.mmio
   if(p(UseBackupMemoryPort)) {
     outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
     VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
@@ -204,7 +197,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     val mem_backup_en = Bool(INPUT)
     val csr = Vec(nTiles, new SmiIO(xLen, csrAddrBits))
     val scr = new SmiIO(xLen, scrAddrBits)
-    val mmio = new NastiIO
     val deviceTree = new NastiIO
   }
 
@@ -307,7 +299,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
   }
 
-  io.mmio <> mmio_ic.io.slaves(addrHashMap("io").port)
   io.deviceTree <> mmio_ic.io.slaves(addrHashMap("conf:devicetree").port)
 
   val mem_channels = mem_ic.io.slaves