riscv/rocket-chip
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tile: don't chain too many unneeded TileLink adapters (#1075)

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Wesley W. Terpstra 2017-10-27 01:12:58 -07:00 committed by GitHub
parent e12bdfdf9b
commit 9f83db998e
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -120,9 +120,9 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
if (xbarPorts.nonEmpty) {
val xbar = LazyModule(new TLXbar)
xbar.node := TLFIFOFixer()(TLFragmenter(xBytes, cacheBlockBytes, earlyAck=true)(slaveNode))
xbar.node := slaveNode
xbarPorts.foreach { case (port, bytes) =>
port := (if (bytes == xBytes) xbar.node else TLFragmenter(bytes, xBytes, earlyAck=true)(TLWidthWidget(xBytes)(xbar.node)))
port := TLFragmenter(bytes, cacheBlockBytes, earlyAck=true)(if (bytes == xBytes) xbar.node else TLWidthWidget(xBytes)(xbar.node))
}
}
}