riscv/rocket-chip
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don't test BRAMSlave for now

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This commit is contained in:
Howard Mao 2016-07-06 15:12:02 -07:00
parent 8625f9ea0c
commit 9f7845f043
1 changed files with 1 additions and 2 deletions
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3
groundtest/src/main/scala/unittest.scala
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@ -568,8 +568,7 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
Module(new TileLinkToSmiConverterTest), Module(new TileLinkToSmiConverterTest),
Module(new AtosConverterTest), Module(new AtosConverterTest),
Module(new NastiMemoryDemuxTest), Module(new NastiMemoryDemuxTest),
Module(new HastiTest), Module(new HastiTest))
Module(new BRAMSlaveTest))
val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3) val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3)
val state = Reg(init = s_idle) val state = Reg(init = s_idle)