riscv/rocket-chip
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don't add io:ext region to address map if no external MMIO

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This commit is contained in:
Howard Mao 2016-07-08 15:29:35 -07:00
parent 35547aa428
commit 9ec55ebb91
2 changed files with 40 additions and 11 deletions
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22
src/main/scala/Configs.scala
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@ -13,6 +13,7 @@ import rocket._
import rocket.Util._ import rocket.Util._
import groundtest._ import groundtest._
import scala.math.max import scala.math.max
import scala.collection.mutable.ListBuffer
import DefaultTestSuites._ import DefaultTestSuites._
import cde.{Parameters, Config, Dump, Knob, CDEMatchError} import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
@ -38,19 +39,28 @@ class BaseConfig extends Config (
lazy val globalAddrMap = { lazy val globalAddrMap = {
val memBase = 0x80000000L val memBase = 0x80000000L
val memSize = 0x80000000L val memSize = 0x80000000L
val ioMap = ListBuffer(AddrMapEntry("int", internalIOAddrMap))
val nMMIOChannels =
site(NExtMMIOAXIChannels) +
site(NExtMMIOAHBChannels) +
site(NExtMMIOTLChannels)
if (nMMIOChannels > 0) {
val extIOBase = 0x60000000L val extIOBase = 0x60000000L
val extIOSize = 0x20000000L val extIOSize = 0x20000000L
val io = AddrMap( ioMap += AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX)))
AddrMapEntry("int", internalIOAddrMap), Dump("IO_BASE", extIOBase)
AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX)))) Dump("IO_SIZE", extIOSize)
}
val addrMap = AddrMap( val addrMap = AddrMap(
AddrMapEntry("io", io), AddrMapEntry("io", new AddrMap(ioMap.toSeq)),
AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))) AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
Dump("MEM_BASE", addrMap("mem").start) Dump("MEM_BASE", addrMap("mem").start)
Dump("MEM_SIZE", memSize) Dump("MEM_SIZE", memSize)
Dump("IO_BASE", addrMap("io:ext").start)
Dump("IO_SIZE", extIOSize)
addrMap addrMap
} }
def makeConfigString() = { def makeConfigString() = {

23
src/main/scala/RocketChip.scala
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@ -115,6 +115,11 @@ object TopUtils {
conv.io.tl <> tl conv.io.tl <> tl
TopUtils.connectNasti(nasti, conv.io.nasti) TopUtils.connectNasti(nasti, conv.io.nasti)
} }
def connectTilelinkAhb(ahb: HastiMasterIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
val bridge = Module(new AHBBridge(true))
bridge.io.tl <> tl
bridge.io.ahb
}
def connectTilelink( def connectTilelink(
outer: ClientUncachedTileLinkIO, inner: ClientUncachedTileLinkIO)(implicit p: Parameters) = { outer: ClientUncachedTileLinkIO, inner: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
outer.acquire <> Queue(inner.acquire) outer.acquire <> Queue(inner.acquire)
@ -277,9 +282,23 @@ class Uncore(implicit val p: Parameters) extends Module
val bootROM = Module(new ROMSlave(TopUtils.makeBootROM())) val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
bootROM.io <> mmioNetwork.port("int:bootrom") bootROM.io <> mmioNetwork.port("int:bootrom")
// The memory map presently has only one external I/O region require(io.mmio_ahb.size + io.mmio_axi.size + io.mmio_tl.size <= 1,
"Maximum of 1 external MMIO channel supported for now")
io.mmio_ahb.foreach { ahb =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost") val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
connectExternalMMIO(ext)(outermostMMIOParams) TopUtils.connectTilelinkAhb(ahb, ext)(outermostMMIOParams)
}
io.mmio_axi.foreach { axi =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelinkNasti(axi, ext)(outermostMMIOParams)
}
io.mmio_tl.foreach { tl =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelink(tl, ext)(outermostMMIOParams)
}
} }
} }