diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 370b4adb..5e420824 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -13,6 +13,7 @@ import rocket._
 import rocket.Util._
 import groundtest._
 import scala.math.max
+import scala.collection.mutable.ListBuffer
 import DefaultTestSuites._
 import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 
@@ -38,19 +39,28 @@ class BaseConfig extends Config (
     lazy val globalAddrMap = {
       val memBase = 0x80000000L
       val memSize = 0x80000000L
-      val extIOBase = 0x60000000L
-      val extIOSize = 0x20000000L
-      val io = AddrMap(
-        AddrMapEntry("int", internalIOAddrMap),
-        AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX))))
+
+      val ioMap = ListBuffer(AddrMapEntry("int", internalIOAddrMap))
+
+      val nMMIOChannels =
+        site(NExtMMIOAXIChannels) +
+        site(NExtMMIOAHBChannels) +
+        site(NExtMMIOTLChannels)
+
+      if (nMMIOChannels > 0) {
+        val extIOBase = 0x60000000L
+        val extIOSize = 0x20000000L
+        ioMap += AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX)))
+        Dump("IO_BASE", extIOBase)
+        Dump("IO_SIZE", extIOSize)
+      }
+
       val addrMap = AddrMap(
-        AddrMapEntry("io", io),
+        AddrMapEntry("io", new AddrMap(ioMap.toSeq)),
         AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
 
       Dump("MEM_BASE", addrMap("mem").start)
       Dump("MEM_SIZE", memSize)
-      Dump("IO_BASE", addrMap("io:ext").start)
-      Dump("IO_SIZE", extIOSize)
       addrMap
     }
     def makeConfigString() = {
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 28e0108a..1f2f4efe 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -115,6 +115,11 @@ object TopUtils {
     conv.io.tl <> tl
     TopUtils.connectNasti(nasti, conv.io.nasti)
   }
+  def connectTilelinkAhb(ahb: HastiMasterIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
+    val bridge = Module(new AHBBridge(true))
+    bridge.io.tl <> tl
+    bridge.io.ahb
+  }
   def connectTilelink(
       outer: ClientUncachedTileLinkIO, inner: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
     outer.acquire <> Queue(inner.acquire)
@@ -277,9 +282,23 @@ class Uncore(implicit val p: Parameters) extends Module
     val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
     bootROM.io <> mmioNetwork.port("int:bootrom")
 
-    // The memory map presently has only one external I/O region
-    val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
-    connectExternalMMIO(ext)(outermostMMIOParams)
+    require(io.mmio_ahb.size + io.mmio_axi.size + io.mmio_tl.size <= 1,
+      "Maximum of 1 external MMIO channel supported for now")
+
+    io.mmio_ahb.foreach { ahb =>
+      val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
+      TopUtils.connectTilelinkAhb(ahb, ext)(outermostMMIOParams)
+    }
+
+    io.mmio_axi.foreach { axi =>
+      val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
+      TopUtils.connectTilelinkNasti(axi, ext)(outermostMMIOParams)
+    }
+
+    io.mmio_tl.foreach { tl =>
+      val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
+      TopUtils.connectTilelink(tl, ext)(outermostMMIOParams)
+    }
   }
 }