riscv/rocket-chip
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don't add io:ext region to address map if no external MMIO

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This commit is contained in:
Howard Mao
2016-07-08 15:29:35 -07:00
parent 35547aa428
commit 9ec55ebb91
2 changed files with 40 additions and 11 deletions
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25
src/main/scala/RocketChip.scala
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@ -115,6 +115,11 @@ object TopUtils {
conv.io.tl <> tl
TopUtils.connectNasti(nasti, conv.io.nasti)
}
def connectTilelinkAhb(ahb: HastiMasterIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
val bridge = Module(new AHBBridge(true))
bridge.io.tl <> tl
bridge.io.ahb
}
def connectTilelink(
outer: ClientUncachedTileLinkIO, inner: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
outer.acquire <> Queue(inner.acquire)
@ -277,9 +282,23 @@ class Uncore(implicit val p: Parameters) extends Module
val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
bootROM.io <> mmioNetwork.port("int:bootrom")
// The memory map presently has only one external I/O region
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
connectExternalMMIO(ext)(outermostMMIOParams)
require(io.mmio_ahb.size + io.mmio_axi.size + io.mmio_tl.size <= 1,
"Maximum of 1 external MMIO channel supported for now")
io.mmio_ahb.foreach { ahb =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelinkAhb(ahb, ext)(outermostMMIOParams)
}
io.mmio_axi.foreach { axi =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelinkNasti(axi, ext)(outermostMMIOParams)
}
io.mmio_tl.foreach { tl =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelink(tl, ext)(outermostMMIOParams)
}
}
}