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Revert "allow MODEL to be something other than TestHarness"

This reverts commit bf253aaa97.
This commit is contained in:
Henry Cook 2016-09-15 11:53:05 -07:00
parent 888f6a2a55
commit 9e2b0aad65
4 changed files with 3 additions and 4 deletions

View File

@ -65,7 +65,7 @@ int main(int argc, char** argv)
srand48(random_seed);
Verilated::randReset(2);
MODEL *tile = new MODEL;
VTestHarness *tile = new VTestHarness;
#if VM_TRACE
Verilated::traceEverOn(true); // Verilator must compute traced signals

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@ -54,7 +54,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
-Wno-STMTDLY --x-assign unique \
-I$(base_dir)/vsrc \
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h -DMODEL=V$(MODEL)"
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
headers = $(wildcard $(base_dir)/csrc/*.h)

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@ -51,7 +51,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
+define+MODEL=$(MODEL) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \

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@ -87,7 +87,7 @@ module TestDriver;
end
end
`MODEL testHarness(
TestHarness testHarness(
.clk(clk),
.reset(reset),
.io_success(success)