From 9e2b0aad65f2b7d3a126f90711577988573ddc4a Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 11:53:05 -0700
Subject: [PATCH] Revert "allow MODEL to be something other than TestHarness"

This reverts commit bf253aaa972964e68e1ac04d12de240bb7ee57df.
---
 csrc/emulator.cc            | 2 +-
 emulator/Makefrag-verilator | 2 +-
 vsim/Makefrag               | 1 -
 vsrc/TestDriver.v           | 2 +-
 4 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index af6e0ac0..db914704 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -65,7 +65,7 @@ int main(int argc, char** argv)
   srand48(random_seed);
 
   Verilated::randReset(2);
-  MODEL *tile = new MODEL;
+  VTestHarness *tile = new VTestHarness;
 
 #if VM_TRACE
   Verilated::traceEverOn(true); // Verilator must compute traced signals
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index 2e4435cb..2cf13f33 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -54,7 +54,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
   +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
 	-Wno-STMTDLY --x-assign unique \
   -I$(base_dir)/vsrc \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h -DMODEL=V$(MODEL)"
+  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
 cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
 headers = $(wildcard $(base_dir)/csrc/*.h)
 
diff --git a/vsim/Makefrag b/vsim/Makefrag
index ba537d85..31ee449b 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -51,7 +51,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \
-	+define+MODEL=$(MODEL) \
 	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \
diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index 305593c0..4d5bd632 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -87,7 +87,7 @@ module TestDriver;
     end
   end
 
-  `MODEL testHarness(
+  TestHarness testHarness(
     .clk(clk),
     .reset(reset),
     .io_success(success)