Revert "allow MODEL to be something other than TestHarness"

This reverts commit bf253aaa97.
2016-09-15 11:53:05 -07:00
parent 888f6a2a55
commit 9e2b0aad65
4 changed files with 3 additions and 4 deletions
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@ -51,7 +51,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \
-	+define+MODEL=$(MODEL) \
 	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \