synchronizers: New chisel ways of cloning type and use simpler lambda function
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@ -107,13 +107,3 @@ object AsyncResetReg {
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def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true), Some(name))
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}
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// While this extends from the SynchronizingShiftRegister
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// classes, it is just a convenience.
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class AsyncResetShiftReg
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object AsyncResetShiftRegister(w: Int = 1, depth: Int = 3) extends AbstractSynchronizerReg(w, depth) {
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override def desiredName = s"AsyncResetShiftReg_w${w}_d{$sync}"
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}
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}
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@ -29,12 +29,12 @@ abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module
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object AbstractSynchronizerReg {
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def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
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val sync_chain = Module(gen(in.getWidth, sync))
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def apply [T <: Chisel.Data](gen: => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
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val sync_chain = Module(gen)
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name.foreach{ sync_chain.suggestName(_) }
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sync_chain.io.d := in.asUInt
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(in.chiselCloneType).fromBits(sync_chain.io.q)
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sync_chain.io.q.asTypeOf(in)
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}
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}
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@ -59,7 +59,7 @@ class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends Abstract
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object AsyncResetSynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
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AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new AsyncResetSynchronizerShiftReg(w, sync)},
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AbstractSynchronizerReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)},
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in, sync, name)
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}
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@ -84,6 +84,6 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchroniz
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object SynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
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AbstractSynchronizerReg(gen = (w: Int, sync: Int) => { new SynchronizerShiftReg(w, sync)},
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AbstractSynchronizerReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)},
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in, sync, name)
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}
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