riscv/rocket-chip
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Made xact_rep an ioValid, removed has_data member

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This commit is contained in:
Henry Cook 2012-03-01 17:03:56 -08:00
parent c7b01230f4
commit 9d7707a0a2
3 changed files with 7 additions and 7 deletions
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2
rocket/src/main/scala/arbiter.scala
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@ -59,9 +59,7 @@ class rocketMemArbiter(n: Int) extends Component {
io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2up(n)-1,0) === UFix(i) io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2up(n)-1,0) === UFix(i)
io.requestor(i).xact_rep.bits.data := io.mem.xact_rep.bits.data io.requestor(i).xact_rep.bits.data := io.mem.xact_rep.bits.data
io.requestor(i).xact_rep.bits.t_type := io.mem.xact_rep.bits.t_type io.requestor(i).xact_rep.bits.t_type := io.mem.xact_rep.bits.t_type
io.requestor(i).xact_rep.bits.has_data := io.mem.xact_rep.bits.has_data
io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2up(n)) io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2up(n))
io.requestor(i).xact_rep.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id io.requestor(i).xact_rep.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
} }
io.mem.xact_rep.ready := Bool(true) // XXX we shouldn't have xact_rep.ready
} }

10
rocket/src/main/scala/coherence.scala
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@ -14,10 +14,9 @@ class MemReqCmd() extends Bundle
val tag = Bits(width = MEM_TAG_BITS) val tag = Bits(width = MEM_TAG_BITS)
} }
class MemResp () extends Bundle class MemResp () extends MemData
{ {
val tag = Bits(width = MEM_TAG_BITS) val tag = Bits(width = MEM_TAG_BITS)
val data = Bits(width = MEM_DATA_BITS)
} }
class ioMem() extends Bundle class ioMem() extends Bundle
@ -72,7 +71,6 @@ class ProbeReplyData extends MemData
class TransactionReply extends MemData { class TransactionReply extends MemData {
val t_type = Bits(width = TTYPE_BITS) val t_type = Bits(width = TTYPE_BITS)
val has_data = Bool()
val tile_xact_id = Bits(width = TILE_XACT_ID_BITS) val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS) val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
} }
@ -88,7 +86,7 @@ class ioTileLink extends Bundle {
val probe_req = (new ioDecoupled) { new ProbeRequest() } val probe_req = (new ioDecoupled) { new ProbeRequest() }
val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
val xact_rep = (new ioDecoupled) { new TransactionReply() } val xact_rep = (new ioValid) { new TransactionReply() }
val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
} }
@ -173,6 +171,10 @@ trait FourStateCoherence extends CoherencePolicy {
} }
state.toBits state.toBits
} }
def replyTypeHasData (reply: TransactionReply): Bool = {
(reply.t_type != X_WRITE_UNCACHED)
}
} }
class XactTracker(id: Int) extends Component with CoherencePolicy { class XactTracker(id: Int) extends Component with CoherencePolicy {

2
rocket/src/main/scala/top.scala
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@ -30,7 +30,7 @@ class Top() extends Component {
// connect tile to hub // connect tile to hub
hub.io.tiles(0).xact_init <> Queue(arbiter.io.mem.xact_init) hub.io.tiles(0).xact_init <> Queue(arbiter.io.mem.xact_init)
hub.io.tiles(0).xact_init_data <> Queue(arbiter.io.mem.xact_init_data) hub.io.tiles(0).xact_init_data <> Queue(arbiter.io.mem.xact_init_data)
arbiter.io.mem.xact_rep <> Queue(hub.io.tiles(0).xact_rep, 1, pipe = true) arbiter.io.mem.xact_rep <> PipeReg(hub.io.tiles(0).xact_rep)
// connect hub to memory // connect hub to memory
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd) io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
io.mem.req_data <> Queue(hub.io.mem.req_data) io.mem.req_data <> Queue(hub.io.mem.req_data)