riscv/rocket-chip
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fix unused set issue for multiple L2 cache banks

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This commit is contained in:
Howard Mao 2015-11-20 23:26:28 -08:00
parent ad3b7fd0e1
commit 9d50f37289
3 changed files with 15 additions and 2 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 4aa954799a0e47d2bc6709417d78856f0968a877 Subproject commit a947d12c4abb51184927b6970babcb397750894a

13
src/main/scala/Configs.scala
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@ -60,17 +60,20 @@ class DefaultConfig extends Config (
case NWays => findBy(CacheName) case NWays => findBy(CacheName)
case RowBits => findBy(CacheName) case RowBits => findBy(CacheName)
case NTLBEntries => findBy(CacheName) case NTLBEntries => findBy(CacheName)
case SetIdxOffset => findBy(CacheName)
case "L1I" => { case "L1I" => {
case NSets => Knob("L1I_SETS") //64 case NSets => Knob("L1I_SETS") //64
case NWays => Knob("L1I_WAYS") //4 case NWays => Knob("L1I_WAYS") //4
case RowBits => 4*site(CoreInstBits) case RowBits => 4*site(CoreInstBits)
case NTLBEntries => 8 case NTLBEntries => 8
case SetIdxOffset => 0
}:PF }:PF
case "L1D" => { case "L1D" => {
case NSets => Knob("L1D_SETS") //64 case NSets => Knob("L1D_SETS") //64
case NWays => Knob("L1D_WAYS") //4 case NWays => Knob("L1D_WAYS") //4
case RowBits => 2*site(CoreDataBits) case RowBits => 2*site(CoreDataBits)
case NTLBEntries => 8 case NTLBEntries => 8
case SetIdxOffset => 0
}:PF }:PF
case ECCCode => None case ECCCode => None
case Replacer => () => new RandomReplacement(site(NWays)) case Replacer => () => new RandomReplacement(site(NWays))
@ -209,6 +212,7 @@ class WithL2Cache extends Config(
site(NWays) site(NWays)
case NWays => Knob("L2_WAYS") case NWays => Knob("L2_WAYS")
case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
case SetIdxOffset => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
}: PartialFunction[Any,Any] }: PartialFunction[Any,Any]
case NAcquireTransactors => 2 case NAcquireTransactors => 2
case NSecondaryMisses => 4 case NSecondaryMisses => 4
@ -229,6 +233,10 @@ class WithL2Capacity256 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" =
class WithL2Capacity128 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 128 }) class WithL2Capacity128 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 128 })
class WithL2Capacity64 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 64 }) class WithL2Capacity64 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 64 })
class With1L2Ways extends Config(knobValues = { case "L2_WAYS" => 1 })
class With2L2Ways extends Config(knobValues = { case "L2_WAYS" => 2 })
class With4L2Ways extends Config(knobValues = { case "L2_WAYS" => 4 })
class DefaultL2Config extends Config(new WithL2Cache ++ new DefaultConfig) class DefaultL2Config extends Config(new WithL2Cache ++ new DefaultConfig)
class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfig) class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfig)
class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig) class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig)
@ -355,3 +363,8 @@ class WithAccumulatorExample extends Config(
class AccumulatorExampleCPPConfig extends Config(new WithAccumulatorExample ++ new DefaultCPPConfig) class AccumulatorExampleCPPConfig extends Config(new WithAccumulatorExample ++ new DefaultCPPConfig)
class AccumulatorExampleVLSIConfig extends Config(new WithAccumulatorExample ++ new DefaultVLSIConfig) class AccumulatorExampleVLSIConfig extends Config(new WithAccumulatorExample ++ new DefaultVLSIConfig)
class SmallL2Config extends Config(
new With4L2Ways ++
new WithL2Capacity128 ++
new DefaultL2Config)

2
uncore

@ -1 +1 @@
Subproject commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b Subproject commit a2409255c361b922aba540578b7c80e9fca33759