diff --git a/rocket b/rocket
index 4aa95479..a947d12c 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 4aa954799a0e47d2bc6709417d78856f0968a877
+Subproject commit a947d12c4abb51184927b6970babcb397750894a
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index b9465fa7..229c2cba 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -60,17 +60,20 @@ class DefaultConfig extends Config (
       case NWays => findBy(CacheName)
       case RowBits => findBy(CacheName)
       case NTLBEntries => findBy(CacheName)
+      case SetIdxOffset => findBy(CacheName)
       case "L1I" => {
         case NSets => Knob("L1I_SETS") //64
         case NWays => Knob("L1I_WAYS") //4
         case RowBits => 4*site(CoreInstBits)
         case NTLBEntries => 8
+        case SetIdxOffset => 0
       }:PF
       case "L1D" => {
         case NSets => Knob("L1D_SETS") //64
         case NWays => Knob("L1D_WAYS") //4
         case RowBits => 2*site(CoreDataBits)
         case NTLBEntries => 8
+        case SetIdxOffset => 0
       }:PF
       case ECCCode => None
       case Replacer => () => new RandomReplacement(site(NWays))
@@ -209,6 +212,7 @@ class WithL2Cache extends Config(
                             site(NWays)
       case NWays => Knob("L2_WAYS")
       case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
+      case SetIdxOffset => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
     }: PartialFunction[Any,Any] 
     case NAcquireTransactors => 2
     case NSecondaryMisses => 4
@@ -229,6 +233,10 @@ class WithL2Capacity256 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" =
 class WithL2Capacity128 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 128 })
 class WithL2Capacity64 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 64 })
 
+class With1L2Ways extends Config(knobValues = { case "L2_WAYS" => 1 })
+class With2L2Ways extends Config(knobValues = { case "L2_WAYS" => 2 })
+class With4L2Ways extends Config(knobValues = { case "L2_WAYS" => 4 })
+
 class DefaultL2Config extends Config(new WithL2Cache ++ new DefaultConfig)
 class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfig)
 class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig)
@@ -355,3 +363,8 @@ class WithAccumulatorExample extends Config(
 
 class AccumulatorExampleCPPConfig extends Config(new WithAccumulatorExample ++ new DefaultCPPConfig)
 class AccumulatorExampleVLSIConfig extends Config(new WithAccumulatorExample ++ new DefaultVLSIConfig)
+
+class SmallL2Config extends Config(
+  new With4L2Ways ++
+  new WithL2Capacity128 ++
+  new DefaultL2Config)
diff --git a/uncore b/uncore
index 1857f36c..a2409255 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b
+Subproject commit a2409255c361b922aba540578b7c80e9fca33759