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Merge pull request #1128 from freechipsproject/chisel_527_fixed

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debug: Remove workaround for Chisel 3 #527
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Megan Wachs 2017-11-27 16:53:02 -08:00 committed by GitHub
commit 9d489c6dcd
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1 changed files with 1 additions and 5 deletions
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src/main/scala/devices/debug/Debug.scala
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@ -521,14 +521,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
DMSTATUSRdData.authenticated := true.B // Not implemented DMSTATUSRdData.authenticated := true.B // Not implemented
DMSTATUSRdData.version := 2.U // Version 0.13 DMSTATUSRdData.version := 2.U // Version 0.13
// Chisel3 Issue #527 , have to do intermediate assignment.
val unavailVec = Wire(init = Vec.fill(nComponents){false.B})
unavailVec := io.debugUnavail
when (selectedHartReg >= nComponents.U) { when (selectedHartReg >= nComponents.U) {
DMSTATUSRdData.allnonexistent := true.B DMSTATUSRdData.allnonexistent := true.B
DMSTATUSRdData.anynonexistent := true.B DMSTATUSRdData.anynonexistent := true.B
}.elsewhen (unavailVec(selectedHartReg)) { }.elsewhen (io.debugUnavail(selectedHartReg)) {
DMSTATUSRdData.allunavail := true.B DMSTATUSRdData.allunavail := true.B
DMSTATUSRdData.anyunavail := true.B DMSTATUSRdData.anyunavail := true.B
}.elsewhen (haltedBitRegs(selectedHartReg)) { }.elsewhen (haltedBitRegs(selectedHartReg)) {