Returned history update to fetch.
- Global history only contains branches. - Only update BHT and history on BTB hits. - Gate off speculative update on stall or icmiss. - Fixed bug where BHT updates were delayed a cycle.
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@ -5,7 +5,6 @@ package rocket
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import Chisel._
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import uncore._
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import Util._
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import Instructions._
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case object NITLBEntries extends Field[Int]
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case object ECCCode extends Field[Option[Code]]
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@ -86,12 +85,10 @@ class Frontend extends FrontendModule
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s2_valid := Bool(false)
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}
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btb.io.req := s1_pc & SInt(-coreInstBytes)
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btb.io.req.valid := !stall && !icmiss
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btb.io.req.bits.addr := s1_pc & SInt(-coreInstBytes)
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btb.io.update := io.cpu.btb_update
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btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
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btb.io.decode.valid := io.cpu.resp.valid && DecodeIsBr(io.cpu.resp.bits.data)
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btb.io.decode.bits.taken := Reg(next=btb.io.resp.bits.taken)
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tlb.io.ptw <> io.cpu.ptw
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tlb.io.req.valid := !stall && !icmiss
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@ -288,21 +285,3 @@ class ICache extends FrontendModule
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}
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}
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}
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object DecodeIsBr {
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def apply(inst: Bits): Bool = {
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val signal = DecodeLogic(inst.toUInt, List(N),
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Array(//JAL -> List(Y),
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//JALR -> List(Y),
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BEQ -> List(Y),
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BNE -> List(Y),
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BGE -> List(Y),
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BGEU -> List(Y),
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BLT -> List(Y),
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BLTU -> List(Y)))
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val (is_br: Bool) :: Nil = signal
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is_br
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}
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}
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