From 9cc35dee9a46dec0c906c976b2ac24d5636d8280 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Mon, 29 Sep 2014 21:41:07 -0700 Subject: [PATCH] Returned history update to fetch. - Global history only contains branches. - Only update BHT and history on BTB hits. - Gate off speculative update on stall or icmiss. - Fixed bug where BHT updates were delayed a cycle. --- rocket/src/main/scala/btb.scala | 69 +++++++++++++++--------------- rocket/src/main/scala/icache.scala | 25 +---------- 2 files changed, 36 insertions(+), 58 deletions(-) diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala index 644b02ee..0f1ee962 100644 --- a/rocket/src/main/scala/btb.scala +++ b/rocket/src/main/scala/btb.scala @@ -47,22 +47,19 @@ class BHTResp extends Bundle with BTBParameters { class BHT(nbht: Int) { val nbhtbits = log2Up(nbht) - def get(addr: UInt): BHTResp = { + def get(addr: UInt, update: Bool): BHTResp = { val res = new BHTResp val index = addr(nbhtbits+1,2) ^ history res.value := table(index) res.history := history + val taken = res.value(0) + when (update) { history := Cat(taken, history(nbhtbits-1,1)) } res } - def updateSpeculativeHistory(taken: Bool): Unit = { - history := Cat(taken, history(nbhtbits-1,1)) - } def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = { val index = addr(nbhtbits+1,2) ^ d.history table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken)) - when (mispredict) { - history := Cat(taken, d.history(nbhtbits-1,1)) - } + when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) } } private val table = Mem(UInt(width = 2), nbht) @@ -88,13 +85,16 @@ class BTBResp extends Bundle with BTBParameters { val bht = new BHTResp } +class BTBReq extends Bundle with BTBParameters { + val addr = UInt(width = vaddrBits) +} + // fully-associative branch target buffer class BTB extends Module with BTBParameters { val io = new Bundle { - val req = UInt(INPUT, vaddrBits) + val req = Valid(new BTBReq).flip val resp = Valid(new BTBResp) val update = Valid(new BTBUpdate).flip - val decode = Valid(new Bundle{val taken = Bool()}).flip val invalidate = Bool(INPUT) } @@ -123,23 +123,23 @@ class BTB extends Module with BTBParameters { idxValid & idxMatch & idxPageMatch } - val update = Pipe(io.update) - val update_target = io.req + val r_update = Pipe(io.update) + val update_target = io.req.bits.addr - val pageHit = pageMatch(io.req) - val hits = tagMatch(io.req, pageHit) - val updatePageHit = pageMatch(update.bits.pc) - val updateHits = tagMatch(update.bits.pc, updatePageHit) + val pageHit = pageMatch(io.req.bits.addr) + val hits = tagMatch(io.req.bits.addr, pageHit) + val updatePageHit = pageMatch(r_update.bits.pc) + val updateHits = tagMatch(r_update.bits.pc, updatePageHit) - private var lfsr = LFSR16(update.valid) + private var lfsr = LFSR16(r_update.valid) def rand(width: Int) = { lfsr = lfsr(lfsr.getWidth-1,1) Random.oneHot(width, lfsr) } - val updateHit = update.bits.prediction.valid - val updateValid = update.bits.incorrectTarget || updateHit && Bool(nBHT > 0) - val updateTarget = updateValid && update.bits.incorrectTarget + val updateHit = r_update.bits.prediction.valid + val updateValid = r_update.bits.incorrectTarget || updateHit && Bool(nBHT > 0) + val updateTarget = updateValid && r_update.bits.incorrectTarget val useUpdatePageHit = updatePageHit.orR val doIdxPageRepl = updateTarget && !useUpdatePageHit @@ -148,7 +148,7 @@ class BTB extends Module with BTBParameters { val idxPageUpdate = OHToUInt(idxPageUpdateOH) val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0)) - val samePage = page(update.bits.pc) === page(update_target) + val samePage = page(r_update.bits.pc) === page(update_target) val usePageHit = (pageHit & ~idxPageReplEn).orR val doTgtPageRepl = updateTarget && !samePage && !usePageHit val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1)) @@ -157,24 +157,24 @@ class BTB extends Module with BTBParameters { val doPageRepl = doIdxPageRepl || doTgtPageRepl val pageReplEn = idxPageReplEn | tgtPageReplEn - idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, nPages)._1) + idxPageRepl := UIntToOH(Counter(r_update.valid && doPageRepl, nPages)._1) - when (update.valid && !(updateValid && !updateTarget)) { + when (r_update.valid && !(updateValid && !updateTarget)) { val nextRepl = Counter(!updateHit && updateValid, entries)._1 - val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl) + val waddr = Mux(updateHit, r_update.bits.prediction.bits.entry, nextRepl) // invalidate entries if we stomp on pages they depend upon idxValid := idxValid & ~Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits idxValid(waddr) := updateValid when (updateTarget) { - assert(io.req === update.bits.target, "BTB request != I$ target") - idxs(waddr) := update.bits.pc + assert(io.req.bits.addr === r_update.bits.target, "BTB request != I$ target") + idxs(waddr) := r_update.bits.pc tgts(waddr) := update_target idxPages(waddr) := idxPageUpdate tgtPages(waddr) := tgtPageUpdate - useRAS(waddr) := update.bits.isReturn - isJump(waddr) := update.bits.isJump + useRAS(waddr) := r_update.bits.isReturn + isJump(waddr) := r_update.bits.isJump } require(nPages % 2 == 0) @@ -185,9 +185,9 @@ class BTB extends Module with BTBParameters { when (en && pageReplEn(i)) { pages(i) := data } writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl), - Mux(idxWritesEven, page(update.bits.pc), page(update_target))) + Mux(idxWritesEven, page(r_update.bits.pc), page(update_target))) writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl), - Mux(idxWritesEven, page(update_target), page(update.bits.pc))) + Mux(idxWritesEven, page(update_target), page(r_update.bits.pc))) when (doPageRepl) { pageValid := pageValid | pageReplEn } } @@ -204,12 +204,11 @@ class BTB extends Module with BTBParameters { if (nBHT > 0) { val bht = new BHT(nBHT) - val res = bht.get(io.req) - when (io.decode.valid) { - bht.updateSpeculativeHistory(io.decode.bits.taken) - } - when (update.valid && !update.bits.isJump) { - bht.update(update.bits.pc, update.bits.prediction.bits.bht, update.bits.taken, update.bits.incorrectTarget) + val res = bht.get(io.req.bits.addr, io.req.valid && hits.orR && !Mux1H(hits, isJump)) + val update_btb_hit = io.update.bits.prediction.valid + when (io.update.valid && update_btb_hit && !io.update.bits.isJump) { + bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht, + io.update.bits.taken, io.update.bits.incorrectTarget) } when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false } io.resp.bits.bht := res diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 4119683d..45327e46 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -5,7 +5,6 @@ package rocket import Chisel._ import uncore._ import Util._ -import Instructions._ case object NITLBEntries extends Field[Int] case object ECCCode extends Field[Option[Code]] @@ -86,12 +85,10 @@ class Frontend extends FrontendModule s2_valid := Bool(false) } - btb.io.req := s1_pc & SInt(-coreInstBytes) + btb.io.req.valid := !stall && !icmiss + btb.io.req.bits.addr := s1_pc & SInt(-coreInstBytes) btb.io.update := io.cpu.btb_update btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate - btb.io.decode.valid := io.cpu.resp.valid && DecodeIsBr(io.cpu.resp.bits.data) - btb.io.decode.bits.taken := Reg(next=btb.io.resp.bits.taken) - tlb.io.ptw <> io.cpu.ptw tlb.io.req.valid := !stall && !icmiss @@ -288,21 +285,3 @@ class ICache extends FrontendModule } } } - -object DecodeIsBr { - def apply(inst: Bits): Bool = { - val signal = DecodeLogic(inst.toUInt, List(N), - Array(//JAL -> List(Y), - //JALR -> List(Y), - BEQ -> List(Y), - BNE -> List(Y), - BGE -> List(Y), - BGEU -> List(Y), - BLT -> List(Y), - BLTU -> List(Y))) - - val (is_br: Bool) :: Nil = signal - is_br - } -} -