refactor PCR file
This commit is contained in:
Andrew Waterman
@ -54,66 +54,101 @@ class rocketDpathBTB(entries: Int) extends Component
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io.target := Mux1H(hits, targets)
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}
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class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle
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{
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val host = new ioHTIF(conf.ntiles)
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val r = new ioReadPort(32, 64)
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val w = new ioWritePort(32, 64)
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val status = Bits(OUTPUT, 32);
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val ptbr = UFix(OUTPUT, PADDR_BITS);
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val evec = UFix(OUTPUT, VADDR_BITS);
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val exception = Bool(INPUT);
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val cause = UFix(INPUT, 6);
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val badvaddr_wen = Bool(INPUT);
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val vec_irq_aux = Bits(INPUT, 64)
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val vec_irq_aux_wen = Bool(INPUT)
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val pc = UFix(INPUT, VADDR_BITS+1);
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val eret = Bool(INPUT);
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val ei = Bool(INPUT);
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val di = Bool(INPUT);
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val ptbr_wen = Bool(OUTPUT);
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val irq_timer = Bool(OUTPUT);
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val irq_ipi = Bool(OUTPUT);
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val replay = Bool(OUTPUT)
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val vecbank = Bits(OUTPUT, 8)
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val vecbankcnt = UFix(OUTPUT, 4)
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val vec_appvl = UFix(INPUT, 12)
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val vec_nxregs = UFix(INPUT, 6)
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val vec_nfregs = UFix(INPUT, 6)
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class Status extends Bundle {
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val im = Bits(width = 8)
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val zero = Bits(width = 7)
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val vm = Bool()
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val s64 = Bool()
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val u64 = Bool()
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val s = Bool()
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val ps = Bool()
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val ec = Bool()
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val ev = Bool()
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val ef = Bool()
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val et = Bool()
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}
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class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
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object PCR
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{
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val io = new ioDpathPCR
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val reg_epc = Reg{Fix()}
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val reg_badvaddr = Reg{Fix()}
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val reg_ebase = Reg{Fix()}
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// commands
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val SZ = 3
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val X = Bits("b???", 3)
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val N = Bits(0,3)
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val F = Bits(1,3) // mfpcr
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val T = Bits(4,3) // mtpcr
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val C = Bits(6,3) // clearpcr
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val S = Bits(7,3) // setpcr
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// regs
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val STATUS = 0
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val EPC = 1
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val BADVADDR = 2
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val EVEC = 3
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val COUNT = 4
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val COMPARE = 5
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val CAUSE = 6
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val PTBR = 7
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val SEND_IPI = 8
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val CLR_IPI = 9
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val COREID = 10
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val IMPL = 11
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val K0 = 12
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val K1 = 13
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val VECBANK = 18
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val VECCFG = 19
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val RESET = 29
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val TOHOST = 30
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val FROMHOST = 31
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}
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class PCR(implicit conf: RocketConfiguration) extends Component
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{
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val io = new Bundle {
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val host = new ioHTIF(conf.ntiles)
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val r = new ioReadPort(conf.nxpr, conf.xprlen)
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val w = new ioWritePort(conf.nxpr, conf.xprlen)
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val status = new Status().asOutput
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val ptbr = UFix(OUTPUT, PADDR_BITS)
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val evec = UFix(OUTPUT, VADDR_BITS)
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val exception = Bool(INPUT)
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val cause = UFix(INPUT, 6)
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val badvaddr_wen = Bool(INPUT)
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val vec_irq_aux = Bits(INPUT, conf.xprlen)
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val vec_irq_aux_wen = Bool(INPUT)
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val pc = UFix(INPUT, VADDR_BITS+1)
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val eret = Bool(INPUT)
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val ei = Bool(INPUT)
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val di = Bool(INPUT)
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val ptbr_wen = Bool(OUTPUT)
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val irq_timer = Bool(OUTPUT)
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val irq_ipi = Bool(OUTPUT)
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val replay = Bool(OUTPUT)
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val vecbank = Bits(OUTPUT, 8)
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val vecbankcnt = UFix(OUTPUT, 4)
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val vec_appvl = UFix(INPUT, 12)
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val vec_nxregs = UFix(INPUT, 6)
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val vec_nfregs = UFix(INPUT, 6)
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}
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import PCR._
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val reg_epc = Reg{Fix(width = VADDR_BITS+1)}
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val reg_badvaddr = Reg{Fix(width = VADDR_BITS+1)}
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val reg_ebase = Reg{Fix(width = VADDR_BITS)}
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val reg_count = WideCounter(32)
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val reg_compare = Reg() { UFix() };
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val reg_cause = Reg() { Bits() };
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val reg_tohost = Reg(resetVal = Bits(0, 64));
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val reg_fromhost = Reg(resetVal = Bits(0, 64));
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val reg_coreid = Reg() { Bits() }
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val reg_k0 = Reg() { Bits() };
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val reg_k1 = Reg() { Bits() };
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val reg_ptbr = Reg() { UFix() };
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val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
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val reg_error_mode = Reg(resetVal = Bool(false));
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val reg_status_vm = Reg(resetVal = Bool(false));
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val reg_status_im = Reg(resetVal = Bits(0,SR_IM_WIDTH));
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val reg_status_sx = Reg(resetVal = Bool(true));
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val reg_status_ux = Reg(resetVal = Bool(true));
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val reg_status_ec = Reg(resetVal = Bool(false));
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val reg_status_ef = Reg(resetVal = Bool(false));
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val reg_status_ev = Reg(resetVal = Bool(false));
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val reg_status_s = Reg(resetVal = Bool(true));
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val reg_status_ps = Reg(resetVal = Bool(false));
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val reg_status_et = Reg(resetVal = Bool(false));
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val r_irq_timer = Reg(resetVal = Bool(false));
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val reg_compare = Reg{Bits(width = 32)}
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val reg_cause = Reg{Bits(width = io.cause.getWidth)}
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val reg_tohost = Reg(resetVal = Bits(0, conf.xprlen))
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val reg_fromhost = Reg(resetVal = Bits(0, conf.xprlen))
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val reg_coreid = Reg{Bits(width = 16)}
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val reg_k0 = Reg{Bits(width = conf.xprlen)}
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val reg_k1 = Reg{Bits(width = conf.xprlen)}
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val reg_ptbr = Reg{UFix(width = PADDR_BITS)}
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val reg_vecbank = Reg(resetVal = Fix(-1,8).toBits)
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val reg_error_mode = Reg(resetVal = Bool(false))
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val reg_status = Reg{new Status} // reset down below
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val r_irq_timer = Reg(resetVal = Bool(false))
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val r_irq_ipi = Reg(resetVal = Bool(true))
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val rdata = Bits();
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@ -127,12 +162,12 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
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val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data)
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io.host.pcr_req.ready := !io.w.en && !io.r.en
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io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR);
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io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
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io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix
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io.ptbr := reg_ptbr;
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io.host.debug.error_mode := reg_error_mode;
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io.r.data := rdata;
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io.status := reg_status
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io.ptbr_wen := wen && waddr === PTBR
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io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix
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io.ptbr := reg_ptbr
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io.host.debug.error_mode := reg_error_mode
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io.r.data := rdata
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io.vecbank := reg_vecbank
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var cnt = UFix(0,4)
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@ -140,7 +175,7 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
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cnt = cnt + reg_vecbank(i)
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io.vecbankcnt := cnt(3,0)
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val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
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val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), io.w.data(conf.xprlen-1,VADDR_BITS).andR, io.w.data(conf.xprlen-1,VADDR_BITS).orR)
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when (io.badvaddr_wen) {
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reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
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}
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@ -149,21 +184,20 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
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}
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when (io.exception) {
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when (!reg_status_et) {
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reg_error_mode := Bool(true)
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}
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.otherwise {
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reg_status_s := Bool(true);
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reg_status_ps := reg_status_s;
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reg_status_et := Bool(false);
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reg_epc := io.pc;
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reg_cause := io.cause;
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when (!reg_status.et) {
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reg_error_mode := true
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}.otherwise {
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reg_status.s := true
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reg_status.ps := reg_status.s
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reg_status.et := false
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reg_epc := io.pc
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reg_cause := io.cause
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}
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}
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when (io.eret) {
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reg_status_s := reg_status_ps;
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reg_status_et := Bool(true);
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reg_status.s := reg_status.ps
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reg_status.et := true
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}
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when (reg_count === reg_compare) {
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@ -172,59 +206,64 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
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io.irq_timer := r_irq_timer;
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io.irq_ipi := r_irq_ipi;
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io.host.ipi_req.valid := io.w.en && io.w.addr === PCR_SEND_IPI
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io.host.ipi_req.valid := io.w.en && io.w.addr === SEND_IPI
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io.host.ipi_req.bits := io.w.data
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io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
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when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === PCR_TOHOST) { reg_tohost := UFix(0) }
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when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === TOHOST) { reg_tohost := UFix(0) }
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val read_impl = Bits(2)
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val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
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val read_veccfg = Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl)
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val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
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rdata := AVec[Bits](
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reg_status.toBits, reg_epc, reg_badvaddr, reg_ebase,
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reg_count, reg_compare, read_cause, read_ptbr,
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reg_coreid/*x*/, read_impl/*x*/, reg_coreid, read_impl,
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reg_k0, reg_k1, reg_k0/*x*/, reg_k1/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
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reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost
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)(raddr)
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when (wen) {
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when (waddr === PCR_STATUS) {
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reg_status_vm := wdata(SR_VM).toBool;
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reg_status_im := wdata(SR_IM_WIDTH+SR_IM,SR_IM);
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reg_status_sx := wdata(SR_S64).toBool;
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reg_status_ux := wdata(SR_U64).toBool;
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reg_status_s := wdata(SR_S).toBool;
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reg_status_ps := wdata(SR_PS).toBool;
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reg_status_ev := Bool(conf.vec) && wdata(SR_EV).toBool;
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reg_status_ef := Bool(conf.fpu) && wdata(SR_EF).toBool;
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reg_status_ec := Bool(conf.rvc) && wdata(SR_EC).toBool;
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reg_status_et := wdata(SR_ET).toBool;
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when (waddr === STATUS) {
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reg_status := new Status().fromBits(wdata)
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reg_status.zero := 0
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if (!conf.vec) reg_status.ev := false
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if (!conf.fpu) reg_status.ef := false
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if (!conf.rvc) reg_status.ec := false
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}
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when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toFix }
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when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; }
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when (waddr === PCR_COUNT) { reg_count := wdata.toUFix }
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when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
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when (waddr === PCR_COREID) { reg_coreid := wdata(15,0) }
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when (waddr === PCR_FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } }
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when (waddr === PCR_TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } }
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when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) }
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when (waddr === PCR_K0) { reg_k0 := wdata; }
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when (waddr === PCR_K1) { reg_k1 := wdata; }
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when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) }
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when (waddr === EPC) { reg_epc := wdata(VADDR_BITS,0).toFix }
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when (waddr === EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; }
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when (waddr === COUNT) { reg_count := wdata.toUFix }
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when (waddr === COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
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when (waddr === COREID) { reg_coreid := wdata(15,0) }
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when (waddr === FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } }
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when (waddr === TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } }
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when (waddr === CLR_IPI) { r_irq_ipi := wdata(0) }
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when (waddr === K0) { reg_k0 := wdata; }
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when (waddr === K1) { reg_k1 := wdata; }
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when (waddr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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when (waddr === VECBANK) { reg_vecbank:= wdata(7,0) }
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}
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io.host.ipi_rep.ready := Bool(true)
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when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
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rdata := io.status // raddr === PCR_STATUS
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switch (raddr) {
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is (PCR_EPC) { rdata := reg_epc }
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is (PCR_BADVADDR) { rdata := reg_badvaddr }
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is (PCR_EVEC) { rdata := reg_ebase }
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is (PCR_COUNT) { rdata := reg_count }
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is (PCR_COMPARE) { rdata := reg_compare }
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is (PCR_CAUSE) { rdata := reg_cause(5) << 63 | reg_cause(4,0) }
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is (PCR_COREID) { rdata := reg_coreid }
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is (PCR_IMPL) { rdata := Bits(2) }
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is (PCR_FROMHOST) { rdata := reg_fromhost; }
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is (PCR_TOHOST) { rdata := reg_tohost; }
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is (PCR_K0) { rdata := reg_k0; }
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is (PCR_K1) { rdata := reg_k1; }
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is (PCR_PTBR) { rdata := reg_ptbr }
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is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
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is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
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when (reset) {
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reg_status.et := false
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reg_status.ef := false
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reg_status.ev := false
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reg_status.ec := false
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reg_status.ps := false
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reg_status.s := true
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reg_status.u64 := true
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reg_status.s64 := true
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reg_status.vm := false
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reg_status.zero := 0
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reg_status.im := 0
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}
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}
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