From 9c857b83f08a257b8c4739ee3ba4dc38c1472e91 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 27 Nov 2012 01:28:06 -0800 Subject: [PATCH] refactor PCR file --- rocket/src/main/scala/consts.scala | 42 --- rocket/src/main/scala/ctrl.scala | 428 ++++++++++++------------- rocket/src/main/scala/dpath.scala | 14 +- rocket/src/main/scala/dpath_util.scala | 271 +++++++++------- rocket/src/main/scala/htif.scala | 5 +- rocket/src/main/scala/package.scala | 1 - rocket/src/main/scala/ptw.scala | 4 +- rocket/src/main/scala/tlb.scala | 14 +- rocket/src/main/scala/util.scala | 5 +- 9 files changed, 388 insertions(+), 396 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 1c40b8ef..9b956260 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -52,48 +52,6 @@ trait ScalarOpConstants { val RA = UFix(1, 5); } -trait PCRConstants { - val PCR_X = Bits("b???", 3) - val PCR_N = Bits(0,3) - val PCR_F = Bits(1,3) // mfpcr - val PCR_T = Bits(4,3) // mtpcr - val PCR_C = Bits(6,3) // clearpcr - val PCR_S = Bits(7,3) // setpcr - - val PCR_STATUS = UFix( 0, 5); - val PCR_EPC = UFix( 1, 5); - val PCR_BADVADDR = UFix( 2, 5); - val PCR_EVEC = UFix( 3, 5); - val PCR_COUNT = UFix( 4, 5); - val PCR_COMPARE = UFix( 5, 5); - val PCR_CAUSE = UFix( 6, 5); - val PCR_PTBR = UFix( 7, 5); - val PCR_SEND_IPI = UFix( 8, 5); - val PCR_CLR_IPI = UFix( 9, 5); - val PCR_COREID = UFix(10, 5); - val PCR_IMPL = UFix(11, 5); - val PCR_K0 = UFix(12, 5); - val PCR_K1 = UFix(13, 5); - val PCR_VECBANK = UFix(18, 5); - val PCR_VECCFG = UFix(19, 5); - val PCR_RESET = UFix(29, 5); - val PCR_TOHOST = UFix(30, 5); - val PCR_FROMHOST = UFix(31, 5); - - // definition of bits in PCR status reg - val SR_ET = 0; // enable traps - val SR_EF = 1; // enable floating point - val SR_EV = 2; // enable vector unit - val SR_EC = 3; // enable compressed instruction encoding - val SR_PS = 4; // mode stack bit - val SR_S = 5; // user/supervisor mode - val SR_U64 = 6; // 64 bit user mode - val SR_S64 = 7; // 64 bit supervisor mode - val SR_VM = 8 // VM enable - val SR_IM = 16 // interrupt mask - val SR_IM_WIDTH = 8 -} - trait InterruptConstants { val CAUSE_INTERRUPT = 32 val IRQ_IPI = 5 diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 28e5ec69..fe2ab61d 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -56,7 +56,7 @@ class ioCtrlDpath extends Bundle() val ex_waddr = UFix(INPUT, 5); // write addr from execute stage val mem_waddr = UFix(INPUT, 5); // write addr from memory stage val wb_waddr = UFix(INPUT, 5); // write addr from writeback stage - val status = Bits(INPUT, 32); + val status = new Status().asInput val fp_sboard_clr = Bool(INPUT); val fp_sboard_clra = UFix(INPUT, 5); val irq_timer = Bool(INPUT); @@ -75,7 +75,7 @@ abstract trait DecodeConstants // | vec_val | | renx1 mem_val | | wen pcr | | | privileged // val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| | | s_wa s_wb | | | | | replay_next // | | | | | | | | | | | | | | | | | | | | | | | | - List(N, X,X,BR_X, X,X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,WA_X, WB_X, PCR_X,N,X,X,X,X) + List(N, X,X,BR_X, X,X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,WA_X, WB_X, PCR.X,N,X,X,X,X) val table: Array[(Bits, List[Bits])] } @@ -89,106 +89,106 @@ object XDecode extends DecodeConstants // | vec_val | | renx1 mem_val | | wen pcr | | | privileged // val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| | | s_wa s_wb | | | | | replay_next // | | | | | | | | | | | | | | | | | | | | | | | | - BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), + BNE-> List(Y, N,N,BR_NE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + BEQ-> List(Y, N,N,BR_EQ, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + BLT-> List(Y, N,N,BR_LT, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + BLTU-> List(Y, N,N,BR_LTU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + BGE-> List(Y, N,N,BR_GE, N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + BGEU-> List(Y, N,N,BR_GEU,N,Y,Y,A2_BTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), - J-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - JAL-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,WA_RA,WB_PC, PCR_N,N,N,N,N,N), - JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N), - JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N), - JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N), - RDNPC-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR_N,N,N,N,N,N), + J-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + JAL-> List(Y, N,N,BR_J, N,N,N,A2_JTYPE,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,WA_RA,WB_PC, PCR.N,N,N,N,N,N), + JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), + JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), + JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), + RDNPC-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), - LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - LH-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - LW-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - LBU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - LHU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SB-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N), - SH-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N), - SW-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N), - SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N), + LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + LH-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + LW-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + LD-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + LBU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + LHU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + LWU-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SB-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), + SH-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), + SW-> List(Y, N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), + SD-> List(xpr64,N,N,BR_N, N,Y,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), - AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), + AMOADD_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOSWAP_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOAND_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOOR_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMIN_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMINU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMAX_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMAXU_W-> List(Y, N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOADD_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOSWAP_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOAND_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOOR_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMIN_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMINU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMAX_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + AMOMAXU_D-> List(xpr64,N,N,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - LUI-> List(Y, N,N,BR_N, N,N,N,A2_LTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - ORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - XORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - riscvAND-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - riscvOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - riscvXOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), + LUI-> List(Y, N,N,BR_N, N,N,N,A2_LTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + ADDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLTI -> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLTIU-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + ANDI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + ORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + XORI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRLI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRAI-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + ADD-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SUB-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLT-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLTU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + riscvAND-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + riscvOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + riscvXOR-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRA-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), + ADDIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRLIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRAIW-> List(xpr64,N,N,BR_N, N,N,Y,A2_ITYPE,DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + ADDW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SUBW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SLLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SL, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SR, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), + MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), - DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), + DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), - SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,Y,N,N), - SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_S,N,N,N,Y,Y), - CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_C,N,N,N,Y,Y), - ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,Y,N,Y,N), - FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,N,N,WA_X, WB_X, PCR_N,Y,N,N,N,Y), - MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_F,N,N,N,Y,Y), - MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_T,N,N,N,Y,Y), - RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_TSC,PCR_N,N,N,N,N,N), - RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_TSC,PCR_N,N,N,N,N,N), - RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_IRT,PCR_N,N,N,N,N,N)) + SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,Y,N,N), + SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.S,N,N,N,Y,Y), + CLEARPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.C,N,N,N,Y,Y), + ERET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,Y,N,Y,N), + FENCE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + FENCE_I-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,N,N,WA_X, WB_X, PCR.N,Y,N,N,N,Y), + MFPCR-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.F,N,N,N,Y,Y), + MTPCR-> List(Y, N,N,BR_N, N,Y,N,A2_RTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.T,N,N,N,Y,Y), + RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_TSC,PCR.N,N,N,N,N,N), + RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_TSC,PCR.N,N,N,N,N,N), + RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_IRT,PCR.N,N,N,N,N,N)) } object FDecode extends DecodeConstants @@ -200,64 +200,64 @@ object FDecode extends DecodeConstants // | vec_val | | renx1 mem_val | | wen pcr | | | privileged // val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| | | s_wa s_wb | | | | | replay_next // | | | | | | | | | | | | | | | | | | | | | | | | - FCVT_S_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_D_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSGNJ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSGNJ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSGNJX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSGNJX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSGNJN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSGNJN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMIN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMIN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMAX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMAX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMUL_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMUL_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FNMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MFTX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MFTX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_WU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_L_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_L_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_LU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_LU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FEQ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FEQ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FLT_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MXTF_S-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MXTF_D-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_D_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_S_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MFFSR-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - MTFSR-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N), - FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N)) + FCVT_S_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_D_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSGNJ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSGNJ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSGNJX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSGNJX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSGNJN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSGNJN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMIN_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMIN_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMAX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMAX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMUL_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMUL_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FNMADD_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MFTX_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MFTX_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_W_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_WU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_WU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_L_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_L_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_LU_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_LU_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FEQ_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FEQ_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FLT_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FLT_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FLE_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FLE_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MXTF_S-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MXTF_D-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_S_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_D_W-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_S_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_D_WU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_S_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_D_L-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_S_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FCVT_D_LU-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MFFSR-> List(Y, Y,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + MTFSR-> List(Y, Y,N,BR_N, N,N,Y,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FLW-> List(Y, Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + FLD-> List(Y, Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + FSW-> List(Y, Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), + FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N)) } object VDecode extends DecodeConstants @@ -269,53 +269,53 @@ object VDecode extends DecodeConstants // | vec_val | | renx1 mem_val | | wen pcr | | | privileged // val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| | | s_wa s_wb | | | | | replay_next // | | | | | | | | | | | | | | | | | | | | | | | | - VVCFGIVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,Y), - VVCFG-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,Y), - VSETVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR_N,N,N,N,N,Y), - VF-> List(Y, N,Y,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_ALU,PCR_N,N,N,N,N,N), - VMVV-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - VMSV-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFMVV-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR_N,N,N,N,N,N), - FENCE_V_L-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - FENCE_V_G-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,N,N), - VLD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLWU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLH-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLHU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLB-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLBU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSH-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSB-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFLD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFLW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFSD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFSW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLSTWU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLSTH-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLSTHU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLSTB-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VLSTBU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSSTH-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VSSTB-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFLSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFLSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFSSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), - VFSSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,N,N), + VVCFGIVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,Y), + VVCFG-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,Y), + VSETVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,Y), + VF-> List(Y, N,Y,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_X, WB_ALU,PCR.N,N,N,N,N,N), + VMVV-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + VMSV-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFMVV-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_RD,WB_X, PCR.N,N,N,N,N,N), + FENCE_V_L-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + FENCE_V_G-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, Y,M_FENCE, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,N,N), + VLD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLWU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLH-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLHU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLB-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLBU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSH-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSB-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFLD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFLW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFSD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFSW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLSTWU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLSTH-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLSTHU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLSTB-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VLSTBU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSSTH-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VSSTB-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFLSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFLSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFSSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), + VFSSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), - VENQCMD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N), - VENQIMM1-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N), - VENQIMM2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N), - VENQCNT-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N), - VXCPTEVAC-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR_N,N,N,N,Y,N), - VXCPTKILL-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,Y,N), - VXCPTHOLD-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR_N,N,N,N,Y,N)) + VENQCMD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,Y,N), + VENQIMM1-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,Y,N), + VENQIMM2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,Y,N), + VENQCNT-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,Y,N), + VXCPTEVAC-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WA_RD,WB_ALU,PCR.N,N,N,N,Y,N), + VXCPTKILL-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,Y,N), + VXCPTHOLD-> List(Y, N,Y,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WA_X, WB_X, PCR.N,N,N,N,Y,N)) } class Control(implicit conf: RocketConfiguration) extends Component @@ -367,7 +367,7 @@ class Control(implicit conf: RocketConfiguration) extends Component val ex_reg_vec_val = Reg(resetVal = Bool(false)) val ex_reg_replay_next = Reg(resetVal = Bool(false)) val ex_reg_load_use = Reg(resetVal = Bool(false)) - val ex_reg_pcr = Reg(resetVal = PCR_N) + val ex_reg_pcr = Reg(resetVal = PCR.N) val ex_reg_br_type = Reg(resetVal = BR_N) val ex_reg_mem_cmd = Reg(){Bits()} val ex_reg_mem_type = Reg(){Bits()} @@ -387,12 +387,12 @@ class Control(implicit conf: RocketConfiguration) extends Component val mem_reg_vec_val = Reg(resetVal = Bool(false)) val mem_reg_replay = Reg(resetVal = Bool(false)) val mem_reg_replay_next = Reg(resetVal = Bool(false)) - val mem_reg_pcr = Reg(resetVal = PCR_N) + val mem_reg_pcr = Reg(resetVal = PCR.N) val mem_reg_cause = Reg(){UFix()} val mem_reg_mem_type = Reg(){Bits()} val wb_reg_valid = Reg(resetVal = Bool(false)) - val wb_reg_pcr = Reg(resetVal = PCR_N) + val wb_reg_pcr = Reg(resetVal = PCR.N) val wb_reg_wen = Reg(resetVal = Bool(false)) val wb_reg_fp_wen = Reg(resetVal = Bool(false)) val wb_reg_flush_inst = Reg(resetVal = Bool(false)) @@ -415,7 +415,7 @@ class Control(implicit conf: RocketConfiguration) extends Component val id_maskable_interrupts = List( (io.dpath.irq_ipi, IRQ_IPI), (io.dpath.irq_timer, IRQ_TIMER)) - var id_interrupts = id_maskable_interrupts.map(i => (io.dpath.status(SR_IM+i._2) && i._1, UFix(CAUSE_INTERRUPT+i._2))) + var id_interrupts = id_maskable_interrupts.map(i => (io.dpath.status.im(i._2) && i._1, UFix(CAUSE_INTERRUPT+i._2))) val (vec_replay, vec_stalld) = if (conf.vec) { // vector control @@ -425,15 +425,15 @@ class Control(implicit conf: RocketConfiguration) extends Component io.vec_iface <> vec.io.iface vec.io.valid := wb_reg_valid - vec.io.s := io.dpath.status(SR_S) - vec.io.sr_ev := io.dpath.status(SR_EV) + vec.io.s := io.dpath.status.s + vec.io.sr_ev := io.dpath.status.ev vec.io.exception := wb_reg_xcpt vec.io.eret := wb_reg_eret val vec_dec = new rocketCtrlVecDecoder() vec_dec.io.inst := io.dpath.inst - val s = io.dpath.status(SR_S) + val s = io.dpath.status.s val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq.ready || !s && io.vec_iface.vcmdq_user_ready val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q.ready || !s && io.vec_iface.vximm1q_user_ready val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q.ready || !s && io.vec_iface.vximm2q_user_ready @@ -455,23 +455,23 @@ class Control(implicit conf: RocketConfiguration) extends Component } else (Bool(false), Bool(false)) val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts) - val id_interrupt = io.dpath.status(SR_ET) && id_interrupt_unmasked + val id_interrupt = io.dpath.status.et && id_interrupt_unmasked def checkExceptions(x: Seq[(Bits, UFix)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) // executing ERET when traps are enabled causes an illegal instruction exception - val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status(SR_ET)) + val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status.et) val (id_xcpt, id_cause) = checkExceptions(List( (id_interrupt, id_interrupt_cause), (io.imem.resp.bits.xcpt_ma, UFix(0)), (io.imem.resp.bits.xcpt_if, UFix(1)), (illegal_inst, UFix(2)), - (id_privileged && !io.dpath.status(SR_S), UFix(3)), - (id_fp_val && !io.dpath.status(SR_EF), UFix(4)), + (id_privileged && !io.dpath.status.s, UFix(3)), + (id_fp_val && !io.dpath.status.ef, UFix(4)), (id_syscall, UFix(6)), - (id_vec_val && !io.dpath.status(SR_EV), UFix(12)))) + (id_vec_val && !io.dpath.status.ev, UFix(12)))) ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid when (id_xcpt) { ex_reg_cause := id_cause } @@ -491,7 +491,7 @@ class Control(implicit conf: RocketConfiguration) extends Component ex_reg_vec_val := Bool(false); ex_reg_replay_next := Bool(false); ex_reg_load_use := Bool(false); - ex_reg_pcr := PCR_N + ex_reg_pcr := PCR.N ex_reg_br_type := BR_N ex_reg_xcpt := Bool(false) } @@ -540,7 +540,7 @@ class Control(implicit conf: RocketConfiguration) extends Component when (ctrl_killx) { mem_reg_valid := Bool(false); - mem_reg_pcr := PCR_N + mem_reg_pcr := PCR.N mem_reg_wen := Bool(false); mem_reg_fp_wen := Bool(false); mem_reg_eret := Bool(false); @@ -574,7 +574,7 @@ class Control(implicit conf: RocketConfiguration) extends Component (mem_reg_mem_val && io.dmem.xcpt.pf.st, UFix(11)))) val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem - val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_vec_val || mem_reg_pcr != PCR_N) + val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_vec_val || mem_reg_pcr != PCR.N) val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem @@ -585,7 +585,7 @@ class Control(implicit conf: RocketConfiguration) extends Component when (ctrl_killm) { wb_reg_valid := Bool(false) - wb_reg_pcr := PCR_N + wb_reg_pcr := PCR.N wb_reg_wen := Bool(false); wb_reg_fp_wen := Bool(false); wb_reg_eret := Bool(false); diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 87454049..0303b552 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -205,8 +205,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Component require(io.dmem.req.bits.tag.getWidth >= 6) // processor control regfile read - val pcr = new rocketDpathPCR() - pcr.io.r.en := io.ctrl.pcr != PCR_N + val pcr = new PCR + pcr.io.r.en := io.ctrl.pcr != PCR.N pcr.io.r.addr := wb_reg_inst(26,22).toUFix pcr.io.host <> io.host @@ -306,7 +306,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component wb_reg_wdata := mem_ll_wdata } wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword, - Mux(io.ctrl.pcr != PCR_N, pcr.io.r.data, + Mux(io.ctrl.pcr != PCR.N, pcr.io.r.data, wb_reg_wdata)) if (conf.vec) @@ -317,7 +317,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component vec.io.ctrl <> io.vec_ctrl io.vec_iface <> vec.io.iface - vec.io.valid := io.ctrl.wb_valid && pcr.io.status(SR_EV) + vec.io.valid := io.ctrl.wb_valid && pcr.io.status.ev vec.io.inst := wb_reg_inst vec.io.vecbank := pcr.io.vecbank vec.io.vecbankcnt := pcr.io.vecbankcnt @@ -341,9 +341,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Component // processor control regfile write pcr.io.w.addr := wb_reg_inst(26,22).toUFix - pcr.io.w.en := io.ctrl.pcr === PCR_T || io.ctrl.pcr === PCR_S || io.ctrl.pcr === PCR_C - pcr.io.w.data := Mux(io.ctrl.pcr === PCR_S, pcr.io.r.data | wb_reg_wdata, - Mux(io.ctrl.pcr === PCR_C, pcr.io.r.data & ~wb_reg_wdata, + pcr.io.w.en := io.ctrl.pcr === PCR.T || io.ctrl.pcr === PCR.S || io.ctrl.pcr === PCR.C + pcr.io.w.data := Mux(io.ctrl.pcr === PCR.S, pcr.io.r.data | wb_reg_wdata, + Mux(io.ctrl.pcr === PCR.C, pcr.io.r.data & ~wb_reg_wdata, wb_reg_wdata)) // hook up I$ diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index d896034a..38b64bb1 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -54,66 +54,101 @@ class rocketDpathBTB(entries: Int) extends Component io.target := Mux1H(hits, targets) } -class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle -{ - val host = new ioHTIF(conf.ntiles) - val r = new ioReadPort(32, 64) - val w = new ioWritePort(32, 64) - - val status = Bits(OUTPUT, 32); - val ptbr = UFix(OUTPUT, PADDR_BITS); - val evec = UFix(OUTPUT, VADDR_BITS); - val exception = Bool(INPUT); - val cause = UFix(INPUT, 6); - val badvaddr_wen = Bool(INPUT); - val vec_irq_aux = Bits(INPUT, 64) - val vec_irq_aux_wen = Bool(INPUT) - val pc = UFix(INPUT, VADDR_BITS+1); - val eret = Bool(INPUT); - val ei = Bool(INPUT); - val di = Bool(INPUT); - val ptbr_wen = Bool(OUTPUT); - val irq_timer = Bool(OUTPUT); - val irq_ipi = Bool(OUTPUT); - val replay = Bool(OUTPUT) - val vecbank = Bits(OUTPUT, 8) - val vecbankcnt = UFix(OUTPUT, 4) - val vec_appvl = UFix(INPUT, 12) - val vec_nxregs = UFix(INPUT, 6) - val vec_nfregs = UFix(INPUT, 6) +class Status extends Bundle { + val im = Bits(width = 8) + val zero = Bits(width = 7) + val vm = Bool() + val s64 = Bool() + val u64 = Bool() + val s = Bool() + val ps = Bool() + val ec = Bool() + val ev = Bool() + val ef = Bool() + val et = Bool() } -class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component +object PCR { - val io = new ioDpathPCR - - val reg_epc = Reg{Fix()} - val reg_badvaddr = Reg{Fix()} - val reg_ebase = Reg{Fix()} + // commands + val SZ = 3 + val X = Bits("b???", 3) + val N = Bits(0,3) + val F = Bits(1,3) // mfpcr + val T = Bits(4,3) // mtpcr + val C = Bits(6,3) // clearpcr + val S = Bits(7,3) // setpcr + + // regs + val STATUS = 0 + val EPC = 1 + val BADVADDR = 2 + val EVEC = 3 + val COUNT = 4 + val COMPARE = 5 + val CAUSE = 6 + val PTBR = 7 + val SEND_IPI = 8 + val CLR_IPI = 9 + val COREID = 10 + val IMPL = 11 + val K0 = 12 + val K1 = 13 + val VECBANK = 18 + val VECCFG = 19 + val RESET = 29 + val TOHOST = 30 + val FROMHOST = 31 +} + +class PCR(implicit conf: RocketConfiguration) extends Component +{ + val io = new Bundle { + val host = new ioHTIF(conf.ntiles) + val r = new ioReadPort(conf.nxpr, conf.xprlen) + val w = new ioWritePort(conf.nxpr, conf.xprlen) + + val status = new Status().asOutput + val ptbr = UFix(OUTPUT, PADDR_BITS) + val evec = UFix(OUTPUT, VADDR_BITS) + val exception = Bool(INPUT) + val cause = UFix(INPUT, 6) + val badvaddr_wen = Bool(INPUT) + val vec_irq_aux = Bits(INPUT, conf.xprlen) + val vec_irq_aux_wen = Bool(INPUT) + val pc = UFix(INPUT, VADDR_BITS+1) + val eret = Bool(INPUT) + val ei = Bool(INPUT) + val di = Bool(INPUT) + val ptbr_wen = Bool(OUTPUT) + val irq_timer = Bool(OUTPUT) + val irq_ipi = Bool(OUTPUT) + val replay = Bool(OUTPUT) + val vecbank = Bits(OUTPUT, 8) + val vecbankcnt = UFix(OUTPUT, 4) + val vec_appvl = UFix(INPUT, 12) + val vec_nxregs = UFix(INPUT, 6) + val vec_nfregs = UFix(INPUT, 6) + } + import PCR._ + + val reg_epc = Reg{Fix(width = VADDR_BITS+1)} + val reg_badvaddr = Reg{Fix(width = VADDR_BITS+1)} + val reg_ebase = Reg{Fix(width = VADDR_BITS)} val reg_count = WideCounter(32) - val reg_compare = Reg() { UFix() }; - val reg_cause = Reg() { Bits() }; - val reg_tohost = Reg(resetVal = Bits(0, 64)); - val reg_fromhost = Reg(resetVal = Bits(0, 64)); - val reg_coreid = Reg() { Bits() } - val reg_k0 = Reg() { Bits() }; - val reg_k1 = Reg() { Bits() }; - val reg_ptbr = Reg() { UFix() }; - val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8)) - - val reg_error_mode = Reg(resetVal = Bool(false)); - val reg_status_vm = Reg(resetVal = Bool(false)); - val reg_status_im = Reg(resetVal = Bits(0,SR_IM_WIDTH)); - val reg_status_sx = Reg(resetVal = Bool(true)); - val reg_status_ux = Reg(resetVal = Bool(true)); - val reg_status_ec = Reg(resetVal = Bool(false)); - val reg_status_ef = Reg(resetVal = Bool(false)); - val reg_status_ev = Reg(resetVal = Bool(false)); - val reg_status_s = Reg(resetVal = Bool(true)); - val reg_status_ps = Reg(resetVal = Bool(false)); - val reg_status_et = Reg(resetVal = Bool(false)); - - val r_irq_timer = Reg(resetVal = Bool(false)); + val reg_compare = Reg{Bits(width = 32)} + val reg_cause = Reg{Bits(width = io.cause.getWidth)} + val reg_tohost = Reg(resetVal = Bits(0, conf.xprlen)) + val reg_fromhost = Reg(resetVal = Bits(0, conf.xprlen)) + val reg_coreid = Reg{Bits(width = 16)} + val reg_k0 = Reg{Bits(width = conf.xprlen)} + val reg_k1 = Reg{Bits(width = conf.xprlen)} + val reg_ptbr = Reg{UFix(width = PADDR_BITS)} + val reg_vecbank = Reg(resetVal = Fix(-1,8).toBits) + val reg_error_mode = Reg(resetVal = Bool(false)) + val reg_status = Reg{new Status} // reset down below + + val r_irq_timer = Reg(resetVal = Bool(false)) val r_irq_ipi = Reg(resetVal = Bool(true)) val rdata = Bits(); @@ -127,12 +162,12 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data) io.host.pcr_req.ready := !io.w.en && !io.r.en - io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR); - io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et); - io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix - io.ptbr := reg_ptbr; - io.host.debug.error_mode := reg_error_mode; - io.r.data := rdata; + io.status := reg_status + io.ptbr_wen := wen && waddr === PTBR + io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix + io.ptbr := reg_ptbr + io.host.debug.error_mode := reg_error_mode + io.r.data := rdata io.vecbank := reg_vecbank var cnt = UFix(0,4) @@ -140,7 +175,7 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component cnt = cnt + reg_vecbank(i) io.vecbankcnt := cnt(3,0) - val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0)) + val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), io.w.data(conf.xprlen-1,VADDR_BITS).andR, io.w.data(conf.xprlen-1,VADDR_BITS).orR) when (io.badvaddr_wen) { reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix; } @@ -149,21 +184,20 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component } when (io.exception) { - when (!reg_status_et) { - reg_error_mode := Bool(true) - } - .otherwise { - reg_status_s := Bool(true); - reg_status_ps := reg_status_s; - reg_status_et := Bool(false); - reg_epc := io.pc; - reg_cause := io.cause; + when (!reg_status.et) { + reg_error_mode := true + }.otherwise { + reg_status.s := true + reg_status.ps := reg_status.s + reg_status.et := false + reg_epc := io.pc + reg_cause := io.cause } } when (io.eret) { - reg_status_s := reg_status_ps; - reg_status_et := Bool(true); + reg_status.s := reg_status.ps + reg_status.et := true } when (reg_count === reg_compare) { @@ -172,59 +206,64 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component io.irq_timer := r_irq_timer; io.irq_ipi := r_irq_ipi; - io.host.ipi_req.valid := io.w.en && io.w.addr === PCR_SEND_IPI + io.host.ipi_req.valid := io.w.en && io.w.addr === SEND_IPI io.host.ipi_req.bits := io.w.data io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready - when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === PCR_TOHOST) { reg_tohost := UFix(0) } + when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === TOHOST) { reg_tohost := UFix(0) } + + val read_impl = Bits(2) + val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS + val read_veccfg = Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) + val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0) + rdata := AVec[Bits]( + reg_status.toBits, reg_epc, reg_badvaddr, reg_ebase, + reg_count, reg_compare, read_cause, read_ptbr, + reg_coreid/*x*/, read_impl/*x*/, reg_coreid, read_impl, + reg_k0, reg_k1, reg_k0/*x*/, reg_k1/*x*/, + reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg, + reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/, + reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/, + reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost + )(raddr) when (wen) { - when (waddr === PCR_STATUS) { - reg_status_vm := wdata(SR_VM).toBool; - reg_status_im := wdata(SR_IM_WIDTH+SR_IM,SR_IM); - reg_status_sx := wdata(SR_S64).toBool; - reg_status_ux := wdata(SR_U64).toBool; - reg_status_s := wdata(SR_S).toBool; - reg_status_ps := wdata(SR_PS).toBool; - reg_status_ev := Bool(conf.vec) && wdata(SR_EV).toBool; - reg_status_ef := Bool(conf.fpu) && wdata(SR_EF).toBool; - reg_status_ec := Bool(conf.rvc) && wdata(SR_EC).toBool; - reg_status_et := wdata(SR_ET).toBool; + when (waddr === STATUS) { + reg_status := new Status().fromBits(wdata) + reg_status.zero := 0 + if (!conf.vec) reg_status.ev := false + if (!conf.fpu) reg_status.ef := false + if (!conf.rvc) reg_status.ec := false } - when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toFix } - when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; } - when (waddr === PCR_COUNT) { reg_count := wdata.toUFix } - when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); } - when (waddr === PCR_COREID) { reg_coreid := wdata(15,0) } - when (waddr === PCR_FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } } - when (waddr === PCR_TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } } - when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) } - when (waddr === PCR_K0) { reg_k0 := wdata; } - when (waddr === PCR_K1) { reg_k1 := wdata; } - when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; } - when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) } + when (waddr === EPC) { reg_epc := wdata(VADDR_BITS,0).toFix } + when (waddr === EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; } + when (waddr === COUNT) { reg_count := wdata.toUFix } + when (waddr === COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); } + when (waddr === COREID) { reg_coreid := wdata(15,0) } + when (waddr === FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } } + when (waddr === TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } } + when (waddr === CLR_IPI) { r_irq_ipi := wdata(0) } + when (waddr === K0) { reg_k0 := wdata; } + when (waddr === K1) { reg_k1 := wdata; } + when (waddr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; } + when (waddr === VECBANK) { reg_vecbank:= wdata(7,0) } } io.host.ipi_rep.ready := Bool(true) when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) } - rdata := io.status // raddr === PCR_STATUS - switch (raddr) { - is (PCR_EPC) { rdata := reg_epc } - is (PCR_BADVADDR) { rdata := reg_badvaddr } - is (PCR_EVEC) { rdata := reg_ebase } - is (PCR_COUNT) { rdata := reg_count } - is (PCR_COMPARE) { rdata := reg_compare } - is (PCR_CAUSE) { rdata := reg_cause(5) << 63 | reg_cause(4,0) } - is (PCR_COREID) { rdata := reg_coreid } - is (PCR_IMPL) { rdata := Bits(2) } - is (PCR_FROMHOST) { rdata := reg_fromhost; } - is (PCR_TOHOST) { rdata := reg_tohost; } - is (PCR_K0) { rdata := reg_k0; } - is (PCR_K1) { rdata := reg_k1; } - is (PCR_PTBR) { rdata := reg_ptbr } - is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) } - is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) } + when (reset) { + reg_status.et := false + reg_status.ef := false + reg_status.ev := false + reg_status.ec := false + reg_status.ps := false + reg_status.s := true + reg_status.u64 := true + reg_status.s64 := true + reg_status.vm := false + reg_status.zero := 0 + reg_status.im := 0 } } diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index c8d203bb..2a777d5e 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -4,6 +4,7 @@ import Chisel._ import Node._ import Constants._ import uncore._ +import Util._ class ioDebug extends Bundle { @@ -199,7 +200,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component val cpu = io.cpu(i) val me = pcr_coreid === UFix(i) - cpu.pcr_req.valid := state === state_pcr_req && me && pcr_addr != PCR_RESET + cpu.pcr_req.valid := state === state_pcr_req && me && pcr_addr != PCR.RESET cpu.pcr_req.bits.rw := cmd === cmd_writecr cpu.pcr_req.bits.addr := pcr_addr cpu.pcr_req.bits.data := pcr_wdata @@ -219,7 +220,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component when (cpu.pcr_req.valid && cpu.pcr_req.ready) { state := state_pcr_resp } - when (state === state_pcr_req && me && pcr_addr === PCR_RESET) { + when (state === state_pcr_req && me && pcr_addr === PCR.RESET) { when (cmd === cmd_writecr) { my_reset := pcr_wdata(0) } diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala index 54492de6..dfc32dd4 100644 --- a/rocket/src/main/scala/package.scala +++ b/rocket/src/main/scala/package.scala @@ -9,7 +9,6 @@ import scala.math._ object Constants extends ScalarOpConstants with uncore.constants.MemoryOpConstants with - PCRConstants with InterruptConstants with RocketDcacheConstants with VectorOpConstants with diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index d8ebdc2f..135b92e0 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -13,14 +13,14 @@ class IOTLBPTW extends Bundle { val perm = Bits(width = PERM_BITS) }).flip - val status = Bits(INPUT, width = 32) + val status = new Status().asInput val invalidate = Bool(INPUT) } class IODatapathPTW extends Bundle { val ptbr = UFix(INPUT, PADDR_BITS) val invalidate = Bool(INPUT) - val status = Bits(INPUT, 32) + val status = new Status().asInput } class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index a6ad8765..101742d3 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -136,22 +136,20 @@ class TLB(entries: Int) extends Component val plru = new PseudoLRU(entries) val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace) - val status_s = io.ptw.status(SR_S) // user/supervisor mode - val status_vm = io.ptw.status(SR_VM) // virtual memory enable val bad_va = io.req.bits.vpn(VPN_BITS) != io.req.bits.vpn(VPN_BITS-1) - val tlb_hit = status_vm && tag_hit - val tlb_miss = status_vm && !tag_hit && !bad_va + val tlb_hit = io.ptw.status.vm && tag_hit + val tlb_miss = io.ptw.status.vm && !tag_hit && !bad_va when (io.req.valid && tlb_hit) { plru.access(OHToUFix(tag_cam.io.hits)) } io.req.ready := state === s_ready - io.resp.xcpt_ld := bad_va || tlb_hit && !Mux(status_s, (sr_array & tag_cam.io.hits).orR, (ur_array & tag_cam.io.hits).orR) - io.resp.xcpt_st := bad_va || tlb_hit && !Mux(status_s, (sw_array & tag_cam.io.hits).orR, (uw_array & tag_cam.io.hits).orR) - io.resp.xcpt_if := bad_va || tlb_hit && !Mux(status_s, (sx_array & tag_cam.io.hits).orR, (ux_array & tag_cam.io.hits).orR) + io.resp.xcpt_ld := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sr_array & tag_cam.io.hits).orR, (ur_array & tag_cam.io.hits).orR) + io.resp.xcpt_st := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sw_array & tag_cam.io.hits).orR, (uw_array & tag_cam.io.hits).orR) + io.resp.xcpt_if := bad_va || tlb_hit && !Mux(io.ptw.status.s, (sx_array & tag_cam.io.hits).orR, (ux_array & tag_cam.io.hits).orR) io.resp.miss := tlb_miss - io.resp.ppn := Mux(status_vm && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(PPN_BITS-1,0)) + io.resp.ppn := Mux(io.ptw.status.vm && !io.req.bits.passthrough, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(PPN_BITS-1,0)) io.resp.hit_idx := tag_cam.io.hits io.ptw.req.valid := state === s_request diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 76f078b2..1b277932 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -14,10 +14,7 @@ object Util object AVec { - def apply[T <: Data](elts: Seq[T]): Vec[T] = { - require(elts.tail.forall(elts.head.getClass == _.getClass)) - Vec(elts) { elts.head.clone } - } + def apply[T <: Data](elts: Seq[T]): Vec[T] = Vec(elts) { elts.head.clone } def apply[T <: Data](elts: Vec[T]): Vec[T] = apply(elts.toSeq) def apply[T <: Data](elt0: T, elts: T*): Vec[T] = apply(elt0 :: elts.toList) }