TL2 WidthWidget (#258)

* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses

src/main/scala/uncore/tilelink2/SRAM.scala

@@ -59,13 +59,14 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
       d_size   := in.a.bits.size
       d_source := in.a.bits.source
       d_addr   := edge.addr_lo(in.a.bits)
-      when (read) {
-        rdata := mem.read(memAddress)
-      } .otherwise {
-        mem.write(memAddress, wdata, in.a.bits.mask.toBools)
-      }
     }
 
+    // exactly this pattern is required to get a RWM memory
+    when (in.a.fire() && !read) {
+      mem.write(memAddress, wdata, in.a.bits.mask.toBools)
+    }
+    rdata := mem.read(memAddress, in.a.fire() && read)
+
     // Tie off unused channels
     in.b.valid := Bool(false)
     in.c.ready := Bool(true)