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TL2 WidthWidget (#258)

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* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
This commit is contained in:
Wesley W. Terpstra
2016-09-08 10:38:38 -07:00
committed by Henry Cook
parent 8536a2a47d
commit 9bfd8c1cf5
6 changed files with 189 additions and 145 deletions
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2
src/main/scala/uncore/tilelink2/Edges.scala
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@ -27,7 +27,7 @@ class TLEdge(
// This gets used everywhere, so make the smallest circuit possible ...
def mask(addr_lo: UInt, lgSize: UInt): UInt = {
val lgBytes = log2Ceil(manager.beatBytes)
val sizeOH = UIntToOH(lgSize, lgBytes)
val sizeOH = UIntToOH(lgSize, log2Up(manager.beatBytes))
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= UInt(lgBytes), Bool(true)))