riscv/rocket-chip
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invalidate I$ prefetcher when invalidating I$

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This commit is contained in:
Andrew Waterman 2012-02-17 17:56:01 -08:00
parent e555fd3fc4
commit 9af86633d7
2 changed files with 6 additions and 0 deletions
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5
rocket/src/main/scala/icache_prefetch.scala
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@ -19,6 +19,7 @@ class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
class ioIPrefetcher extends Bundle() { class ioIPrefetcher extends Bundle() {
val icache = new ioICache(); val icache = new ioICache();
val mem = new ioIPrefetcherMem(); val mem = new ioIPrefetcherMem();
val invalidate = Bool(INPUT)
} }
class rocketIPrefetcher extends Component() { class rocketIPrefetcher extends Component() {
@ -84,6 +85,10 @@ class rocketIPrefetcher extends Component() {
when (fill_done.toBool & ip_mem_resp_val.toBool) { state := s_req_wait; } when (fill_done.toBool & ip_mem_resp_val.toBool) { state := s_req_wait; }
} }
} }
when (io.invalidate) {
state := s_invalid
}
} }
} }

1
rocket/src/main/scala/top.scala
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@ -30,6 +30,7 @@ class Top() extends Component {
cpu.io.debug <> io.debug; cpu.io.debug <> io.debug;
cpu.io.console <> io.console; cpu.io.console <> io.console;
icache_pf.io.invalidate := cpu.io.imem.invalidate
icache.io.mem <> icache_pf.io.icache; icache.io.mem <> icache_pf.io.icache;
cpu.io.imem <> icache.io.cpu; cpu.io.imem <> icache.io.cpu;
cpu.io.vimem <> vicache.io.cpu; cpu.io.vimem <> vicache.io.cpu;