riscv/rocket-chip
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rocket: support asynchronous external busses

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This commit is contained in:
Wesley W. Terpstra
2016-07-18 14:09:10 -07:00
committed by Howard Mao
parent 19b44ec95b
commit 9ae23f18bd
3 changed files with 26 additions and 5 deletions
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4
src/main/scala/Configs.scala
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@ -191,6 +191,7 @@ class BaseConfig extends Config (
case UseVM => true
case UseUser => true
case UseDebug => true
case AsyncDebugBus => false
case NBreakpoints => 1
case UsePerfCounters => true
case FastLoadWord => true
@ -216,6 +217,7 @@ class BaseConfig extends Config (
true
}
case NExtInterrupts => 2
case AsyncMMIOChannels => false
case ExtMMIOPorts => AddrMap()
/*
AddrMap(
@ -225,6 +227,7 @@ class BaseConfig extends Config (
case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
@ -297,6 +300,7 @@ class BaseConfig extends Config (
}
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
case AsyncMemChannels => false
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case TMemoryChannels => BusType.AXI
case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")