riscv/rocket-chip
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Don't include RV64 instructions in RV32 decode table

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This commit is contained in:
Andrew Waterman
2016-05-25 14:26:45 -07:00
parent 4605b616c1
commit 9aa724706e
2 changed files with 229 additions and 233 deletions
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14
rocket/src/main/scala/rocket.scala
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@ -120,11 +120,15 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
val rocc = new RoCCInterface().flip
}
var decode_table = new XDecode().table
if (usingAtomics) decode_table ++= new ADecode().table
if (usingFPU) decode_table ++= new FDecode().table
if (usingFPU && usingFDivSqrt) decode_table ++= new FDivSqrtDecode().table
if (usingRoCC) decode_table ++= new RoCCDecode().table
val decode_table = {
(if (true) new MDecode +: (if (xLen > 32) Seq(new M64Decode) else Nil) else Nil) ++:
(if (usingAtomics) new ADecode +: (if (xLen > 32) Seq(new A64Decode) else Nil) else Nil) ++:
(if (usingFPU) new FDecode +: (if (xLen > 32) Seq(new F64Decode) else Nil) else Nil) ++:
(if (usingFPU && usingFDivSqrt) Some(new FDivSqrtDecode) else None) ++:
(if (usingRoCC) Some(new RoCCDecode) else None) ++:
(if (xLen > 32) Some(new I64Decode) else None) ++:
Seq(new IDecode)
} flatMap(_.table)
val ex_ctrl = Reg(new IntCtrlSigs)
val mem_ctrl = Reg(new IntCtrlSigs)