only instantiate VI$ if HAVE_VEC
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@ -19,16 +19,23 @@ class Top() extends Component {
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val cpu = new rocketProc();
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val cpu = new rocketProc();
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val icache = new rocketICache(128, 2); // 128 sets x 2 ways
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val icache = new rocketICache(128, 2); // 128 sets x 2 ways
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val icache_pf = new rocketIPrefetcher();
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val icache_pf = new rocketIPrefetcher();
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val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
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val dcache = new HellaCacheUniproc();
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val dcache = new HellaCacheUniproc();
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val arbiter = new rocketMemArbiter(4);
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val arbiter = new rocketMemArbiter(4);
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arbiter.io.requestor(0) <> dcache.io.mem
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arbiter.io.requestor(0) <> dcache.io.mem
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arbiter.io.requestor(1) <> icache_pf.io.mem
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arbiter.io.requestor(1) <> icache_pf.io.mem
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arbiter.io.requestor(2) <> vicache.io.mem
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arbiter.io.requestor(3) <> htif.io.mem
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arbiter.io.requestor(3) <> htif.io.mem
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arbiter.io.mem <> io.mem
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arbiter.io.mem <> io.mem
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if (HAVE_VEC)
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{
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val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
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arbiter.io.requestor(2) <> vicache.io.mem
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cpu.io.vimem <> vicache.io.cpu;
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}
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else
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arbiter.io.requestor(2).req_val := Bool(false)
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htif.io.host <> io.host
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htif.io.host <> io.host
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cpu.io.host <> htif.io.cpu(0);
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cpu.io.host <> htif.io.cpu(0);
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cpu.io.debug <> io.debug;
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cpu.io.debug <> io.debug;
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@ -36,7 +43,6 @@ class Top() extends Component {
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icache_pf.io.invalidate := cpu.io.imem.invalidate
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icache_pf.io.invalidate := cpu.io.imem.invalidate
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icache.io.mem <> icache_pf.io.icache;
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icache.io.mem <> icache_pf.io.icache;
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cpu.io.imem <> icache.io.cpu;
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cpu.io.imem <> icache.io.cpu;
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cpu.io.vimem <> vicache.io.cpu;
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cpu.io.dmem <> dcache.io.cpu;
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cpu.io.dmem <> dcache.io.cpu;
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}
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}
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