riscv/rocket-chip
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rocket: remove hard-coded paddrBits (#610)

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Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
This commit is contained in:
Henry Cook 2017-03-24 22:30:18 -07:00 committed by Wesley W. Terpstra
parent 19485a9861
commit 996a31364a
3 changed files with 3 additions and 2 deletions
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1
src/main/scala/coreplex/RocketTiles.scala
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@ -31,7 +31,6 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
case TileKey => c case TileKey => c
case BuildRoCC => c.rocc case BuildRoCC => c.rocc
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0) case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
} }
// Hack debug interrupt into a node (future debug module should use diplomacy) // Hack debug interrupt into a node (future debug module should use diplomacy)

2
src/main/scala/rocket/Tile.scala
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@ -119,6 +119,8 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
with CanHaveLegacyRoccsModule with CanHaveLegacyRoccsModule
with CanHaveScratchpadModule { with CanHaveScratchpadModule {
require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits)
val core = Module(p(BuildCore)(outer.p)) val core = Module(p(BuildCore)(outer.p))
core.io.hartid := io.hartid core.io.hartid := io.hartid
outer.frontend.module.io.cpu <> core.io.imem outer.frontend.module.io.cpu <> core.io.imem

2
src/main/scala/tile/Core.scala
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@ -52,7 +52,7 @@ trait HasCoreParameters extends HasTileParameters {
def pgIdxBits = 12 def pgIdxBits = 12
def pgLevelBits = 10 - log2Ceil(xLen / 32) def pgLevelBits = 10 - log2Ceil(xLen / 32)
def vaddrBits = pgIdxBits + pgLevels * pgLevelBits def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
val paddrBits = 32//p(PAddrBits) val paddrBits = p(PAddrBits)
def ppnBits = paddrBits - pgIdxBits def ppnBits = paddrBits - pgIdxBits
def vpnBits = vaddrBits - pgIdxBits def vpnBits = vaddrBits - pgIdxBits
val pgLevels = p(PgLevels) val pgLevels = p(PgLevels)