From 996a31364ac71d56d1eae4d18ac9d319a7b12d2c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 24 Mar 2017 22:30:18 -0700 Subject: [PATCH] rocket: remove hard-coded paddrBits (#610) Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port. --- src/main/scala/coreplex/RocketTiles.scala | 1 - src/main/scala/rocket/Tile.scala | 2 ++ src/main/scala/tile/Core.scala | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala index 7f7493e2..eba2291b 100644 --- a/src/main/scala/coreplex/RocketTiles.scala +++ b/src/main/scala/coreplex/RocketTiles.scala @@ -31,7 +31,6 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { case TileKey => c case BuildRoCC => c.rocc case SharedMemoryTLEdge => l1tol2.node.edgesIn(0) - case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits } // Hack debug interrupt into a node (future debug module should use diplomacy) diff --git a/src/main/scala/rocket/Tile.scala b/src/main/scala/rocket/Tile.scala index ec882cf8..2d089ae7 100644 --- a/src/main/scala/rocket/Tile.scala +++ b/src/main/scala/rocket/Tile.scala @@ -119,6 +119,8 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne with CanHaveLegacyRoccsModule with CanHaveScratchpadModule { + require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits) + val core = Module(p(BuildCore)(outer.p)) core.io.hartid := io.hartid outer.frontend.module.io.cpu <> core.io.imem diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index 7646ce20..3212ac77 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -52,7 +52,7 @@ trait HasCoreParameters extends HasTileParameters { def pgIdxBits = 12 def pgLevelBits = 10 - log2Ceil(xLen / 32) def vaddrBits = pgIdxBits + pgLevels * pgLevelBits - val paddrBits = 32//p(PAddrBits) + val paddrBits = p(PAddrBits) def ppnBits = paddrBits - pgIdxBits def vpnBits = vaddrBits - pgIdxBits val pgLevels = p(PgLevels)