riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rocket: remove hard-coded paddrBits (#610)

Browse Source 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
This commit is contained in:
Henry Cook
2017-03-24 22:30:18 -07:00
committed by Wesley W. Terpstra
parent 19485a9861
commit 996a31364a
3 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/tile/Core.scala
View File

@ -52,7 +52,7 @@ trait HasCoreParameters extends HasTileParameters {
def pgIdxBits = 12
def pgLevelBits = 10 - log2Ceil(xLen / 32)
def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
val paddrBits = 32//p(PAddrBits)
val paddrBits = p(PAddrBits)
def ppnBits = paddrBits - pgIdxBits
def vpnBits = vaddrBits - pgIdxBits
val pgLevels = p(PgLevels)