riscv/rocket-chip
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rocket: remove hard-coded paddrBits (#610)

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Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
This commit is contained in:
Henry Cook
2017-03-24 22:30:18 -07:00
committed by Wesley W. Terpstra
parent 19485a9861
commit 996a31364a
3 changed files with 3 additions and 2 deletions
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src/main/scala/rocket/Tile.scala
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@ -119,6 +119,8 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
with CanHaveLegacyRoccsModule
with CanHaveScratchpadModule {
require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits)
val core = Module(p(BuildCore)(outer.p))
core.io.hartid := io.hartid
outer.frontend.module.io.cpu <> core.io.imem