riscv/rocket-chip
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rocket: remove hard-coded paddrBits (#610)

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Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
This commit is contained in:
Henry Cook
2017-03-24 22:30:18 -07:00
committed by Wesley W. Terpstra
parent 19485a9861
commit 996a31364a
3 changed files with 3 additions and 2 deletions
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src/main/scala/coreplex/RocketTiles.scala
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@ -31,7 +31,6 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
case TileKey => c
case BuildRoCC => c.rocc
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
}
// Hack debug interrupt into a node (future debug module should use diplomacy)