riscv/rocket-chip
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Point to correct Chisel commit

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This commit is contained in:
Andrew Waterman 2015-10-01 10:31:29 -07:00
parent a76f0bf8fb
commit 996670a4a6
3 changed files with 3 additions and 2 deletions
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2
chisel

@ -1 +1 @@
Subproject commit ededc302ed1fc9ba9d583cf32d50deec55683952 Subproject commit d3e0c01512b61cf4755b1d6b99b7e8865514689a

1
emulator/Makefile
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@ -7,6 +7,7 @@ sim_dir = .
output_dir = $(sim_dir)/output output_dir = $(sim_dir)/output
BACKEND = c BACKEND = c
#CONFIG ?= ZscaleConfig
CONFIG ?= DefaultCPPConfig CONFIG ?= DefaultCPPConfig
include $(base_dir)/Makefrag include $(base_dir)/Makefrag

2
fpga-zynq

@ -1 +1 @@
Subproject commit eb82eb8b80495a48fd2e23a969fd6725b1e12e29 Subproject commit 2bf892b5ba22661d925bc8c1fb2cbaf091b1d6ad