Merge pull request #749 from freechipsproject/unit-test-speedup

Unit test speedup

regression/Makefile

@@ -66,7 +66,7 @@ endif
 
 ifeq ($(SUITE),UnittestSuite)
 PROJECT=unittest
-CONFIGS=UncoreUnitTestConfig TLSimpleUnitTestConfig TLWidthUnitTestConfig TLXbarUnitTestConfig
+CONFIGS=UncoreUnitTestConfig TLSimpleUnitTestConfig TLWidthUnitTestConfig
 endif
 
 ifeq ($(SUITE), JtagDtmSuite)

src/main/scala/uncore/ahb/Test.scala

@@ -16,9 +16,9 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter
   new AHBRegBundle((), _)    with RRTest1Bundle)(
   new AHBRegModule((), _, _) with RRTest1Module)
 
-class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AHBFuzzNative"))
   var xbar  = LazyModule(new AHBFanout)
   val ram   = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
@@ -34,15 +34,15 @@ class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBNativeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+class AHBNativeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AHBFuzzNative(aFlow)).module)
+  val dut = Module(LazyModule(new AHBFuzzNative(aFlow, txns)).module)
   io.finished := dut.io.finished
 }
 
-class AHBFuzzMaster(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
   val node  = AHBOutputNode()
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
 
   model.node := fuzz.node
@@ -83,9 +83,9 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class AHBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val master = LazyModule(new AHBFuzzMaster(aFlow))
+  val master = LazyModule(new AHBFuzzMaster(aFlow, txns))
   val slave  = LazyModule(new AHBFuzzSlave)
 
   slave.node := master.node
@@ -95,7 +95,7 @@ class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+class AHBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AHBFuzzBridge(aFlow)).module)
+  val dut = Module(LazyModule(new AHBFuzzBridge(aFlow, txns)).module)
   io.finished := dut.io.finished
 }

src/main/scala/uncore/apb/Test.scala

@@ -16,9 +16,9 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends APBRegisterRouter
   new APBRegBundle((), _)    with RRTest1Bundle)(
   new APBRegModule((), _, _) with RRTest1Module)
 
-class APBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
+class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("APBFuzzMaster"))
   var xbar  = LazyModule(new APBFanout)
   val ram   = LazyModule(new APBRAM(AddressSet(0x0, 0xff)))
@@ -39,7 +39,7 @@ class APBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class APBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+class APBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new APBFuzzBridge(aFlow)).module)
+  val dut = Module(LazyModule(new APBFuzzBridge(aFlow, txns)).module)
   io.finished := dut.io.finished
 }

src/main/scala/uncore/axi4/Test.scala

@@ -16,9 +16,9 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRoute
   new AXI4RegBundle((), _)    with RRTest1Bundle)(
   new AXI4RegModule((), _, _) with RRTest1Module)
 
-class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
+class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
   val xbar  = LazyModule(new TLXbar)
   val gpio  = LazyModule(new RRTest1(0x400))
@@ -34,14 +34,14 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4LiteFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
+class AXI4LiteFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AXI4LiteFuzzRAM).module)
+  val dut = Module(LazyModule(new AXI4LiteFuzzRAM(txns)).module)
   io.finished := dut.io.finished
 }
 
-class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
+class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
   val xbar  = LazyModule(new TLXbar)
   val gpio  = LazyModule(new RRTest0(0x400))
@@ -57,8 +57,8 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4FullFuzzRAMTest(implicit p: Parameters) extends UnitTest(500000) {
+class AXI4FullFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AXI4FullFuzzRAM).module)
+  val dut = Module(LazyModule(new AXI4FullFuzzRAM(txns)).module)
   io.finished := dut.io.finished
 }
 
@@ -66,10 +66,10 @@ trait HasFuzzTarget {
   val fuzzAddr = AddressSet(0x0, 0xfff)
 }
 
-class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
+class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with HasFuzzTarget
 {
   val node  = AXI4OutputNode()
-  val fuzz  = LazyModule(new TLFuzzer(5000, overrideAddress = Some(fuzzAddr)))
+  val fuzz  = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
   val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
 
   model.node := fuzz.node
@@ -120,9 +120,9 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
   }
 }
 
-class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule
+class AXI4FuzzBridge(txns: Int)(implicit p: Parameters) extends LazyModule
 {
-  val master = LazyModule(new AXI4FuzzMaster)
+  val master = LazyModule(new AXI4FuzzMaster(txns))
   val slave  = LazyModule(new AXI4FuzzSlave)
 
   slave.node := master.node
@@ -132,7 +132,7 @@ class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AXI4BridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
+class AXI4BridgeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new AXI4FuzzBridge).module)
+  val dut = Module(LazyModule(new AXI4FuzzBridge(txns)).module)
   io.finished := dut.io.finished
 }

src/main/scala/uncore/devices/Rom.scala

@@ -88,7 +88,7 @@ class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
     data = rdata)
 }
 
-class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
+class ROMSlaveTest(timeout: Int = 4096)(implicit p: Parameters) extends UnitTest(timeout) {
   val romdata = Seq(
     BigInt("01234567deadbeef", 16),
     BigInt("ab32fee8d00dfeed", 16))

src/main/scala/uncore/tilelink2/Arbiter.scala

@@ -94,7 +94,7 @@ object TLArbiter
 /** Synthesizeable unit tests */
 import unittest._
 
-class TestRobin()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TestRobin(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   val sources = Wire(Vec(6, DecoupledIO(UInt(width=3))))
   val sink = Wire(DecoupledIO(UInt(width=3)))
   val count = RegInit(UInt(0, width=8))
@@ -117,5 +117,5 @@ class TestRobin()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
   when (!sink.fire()) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
 
   count := count + UInt(1)
-  io.finished := count >= UInt(128)
+  io.finished := count >= UInt(txns)
 }

src/main/scala/uncore/tilelink2/AsyncCrossing.scala

@@ -137,10 +137,10 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) ext
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
+class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
   val model = LazyModule(new TLRAMModel("AsyncCrossing"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val cross = LazyModule(new TLAsyncCrossing)
 
   model.node := fuzz.node
@@ -168,6 +168,6 @@ class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMAsyncCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAsyncCrossing).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMAsyncCrossing(txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/AtomicAutomata.scala

@@ -293,8 +293,8 @@ import unittest._
 
 //TODO ensure handler will pass through operations to clients that can handle them themselves
 
-class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
+class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AtomicAutomata"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
@@ -306,6 +306,6 @@ class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMAtomicAutomataTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMAtomicAutomata).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMAtomicAutomata(txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/Fragmenter.scala

@@ -286,8 +286,8 @@ object TLFragmenter
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends LazyModule {
+class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("Fragmenter"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
@@ -309,6 +309,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) e
   }
 }
 
-class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize)).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/Fuzzer.scala

@@ -211,7 +211,7 @@ class TLFuzzer(
 /** Synthesizeable integration test */
 import unittest._
 
-class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
+class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
 {
   val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
@@ -219,7 +219,7 @@ class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
   val gpio = LazyModule(new RRTest1(0x400))
   val xbar = LazyModule(new TLXbar)
   val xbar2= LazyModule(new TLXbar)
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val cross = LazyModule(new TLAsyncCrossing)
 
   model.node := fuzz.node
@@ -251,7 +251,7 @@ class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class TLFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
+class TLFuzzRAMTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new TLFuzzRAM).module)
+  val dut = Module(LazyModule(new TLFuzzRAM(txns)).module)
   io.finished := dut.io.finished
 }

src/main/scala/uncore/tilelink2/HintHandler.scala

@@ -110,8 +110,8 @@ import unittest._
 
 //TODO ensure handler will pass through hints to clients that can handle them themselves
 
-class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
+class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("HintHandler"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
@@ -123,6 +123,6 @@ class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMHintHandlerTest()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMHintHandlerTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMHintHandler).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMHintHandler(txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/Nodes.scala

@@ -106,7 +106,7 @@ case class TLInternalInputNode(portParams: Seq[TLClientPortParameters]) extends
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLInputNodeTest()(implicit p: Parameters) extends UnitTest(500000) {
+class TLInputNodeTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
   class Acceptor extends LazyModule {
     val node = TLInputNode()
     val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
@@ -119,7 +119,7 @@ class TLInputNodeTest()(implicit p: Parameters) extends UnitTest(500000) {
     }
   }
 
-  val fuzzer = LazyModule(new TLFuzzer(5000))
+  val fuzzer = LazyModule(new TLFuzzer(txns))
   LazyModule(new Acceptor).node := TLFragmenter(4, 64)(fuzzer.node)
 
   io.finished := Module(fuzzer.module).io.finished

src/main/scala/uncore/tilelink2/RationalCrossing.scala

@@ -149,9 +149,9 @@ class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: P
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMRationalCrossingSource(name: String)(implicit p: Parameters) extends LazyModule {
+class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameters) extends LazyModule {
   val node = TLRationalOutputNode()
-  val fuzz  = LazyModule(new TLFuzzer(5000))
+  val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel(name))
 
   model.node := fuzz.node
@@ -179,20 +179,20 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame
   }
 }
 
-class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule {
+class TLRAMRationalCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
-  val sym_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_fast"))
+  val sym_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_fast", txns))
   val sym_slow_sink   = LazyModule(new TLRAMRationalCrossingSink(Symmetric))
   sym_slow_sink.node := sym_fast_source.node
 
-  val sym_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_slow"))
+  val sym_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_slow", txns))
   val sym_fast_sink   = LazyModule(new TLRAMRationalCrossingSink(Symmetric))
   sym_fast_sink.node := sym_slow_source.node
 
-  val fix_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing fast"))
+  val fix_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing fast", txns))
   val fix_slow_sink   = LazyModule(new TLRAMRationalCrossingSink(FastToSlow))
   fix_slow_sink.node := fix_fast_source.node
 
-  val fix_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing slow"))
+  val fix_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing slow", txns))
   val fix_fast_sink   = LazyModule(new TLRAMRationalCrossingSink(SlowToFast))
   fix_fast_sink.node := fix_slow_source.node
 
@@ -222,6 +222,6 @@ class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMRationalCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMRationalCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMRationalCrossing).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMRationalCrossing(txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/RegisterRouterTest.scala

@@ -255,8 +255,8 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(
   new TLRegBundle((), _)    with RRTest1Bundle)(
   new TLRegModule((), _, _) with RRTest1Module)
 
-class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
+class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val rrtr = LazyModule(new RRTest0(0x400))
 
   rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
@@ -266,12 +266,12 @@ class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRR0Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRR0Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest0).module).io.finished
+  io.finished := Module(LazyModule(new FuzzRRTest0(txns)).module).io.finished
 }
 
-class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
+class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val rrtr = LazyModule(new RRTest1(0x400))
 
   rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
@@ -281,7 +281,7 @@ class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRR1Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRR1Test(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new FuzzRRTest1).module).io.finished
+  io.finished := Module(LazyModule(new FuzzRRTest1(txns)).module).io.finished
 }
 

src/main/scala/uncore/tilelink2/SRAM.scala

@@ -91,8 +91,8 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
 /** Synthesizeable unit testing */
 import unittest._
 
-class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
+class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("SRAMSimple"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
@@ -104,6 +104,6 @@ class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule
   }
 }
 
-class TLRAMSimpleTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMSimpleTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes)).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes, txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/TestRAM.scala

@@ -65,8 +65,8 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
 /** Synthesizeable unit testing */
 import unittest._
 
-class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
+class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("ZeroDelay"))
   val ram  = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
@@ -78,6 +78,6 @@ class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModu
   }
 }
 
-class TLRAMZeroDelayTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMZeroDelayTest(ramBeatBytes: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes)).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes, txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/WidthWidget.scala

@@ -180,8 +180,8 @@ object TLWidthWidget
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends LazyModule {
+class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("WidthWidget"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
@@ -197,6 +197,6 @@ class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends
   }
 }
 
-class TLRAMWidthWidgetTest(little: Int, big: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big)).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module).io.finished
 }

src/main/scala/uncore/tilelink2/Xbar.scala

@@ -213,8 +213,8 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
 /** Synthesizeable unit tests */
 import unittest._
 
-class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
+class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
-  val fuzz = LazyModule(new TLFuzzer(5000))
+  val fuzz = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("Xbar"))
   val xbar = LazyModule(new TLXbar)
 
@@ -230,15 +230,15 @@ class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
   }
 }
 
-class TLRAMXbarTest(nManagers: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
+class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLRAMXbar(nManagers)).module).io.finished
+  io.finished := Module(LazyModule(new TLRAMXbar(nManagers,txns)).module).io.finished
 }
 
-class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) extends LazyModule {
+class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
   val xbar = LazyModule(new TLXbar)
 
   val fuzzers = (0 until nClients) map { n =>
-    val fuzz = LazyModule(new TLFuzzer(5000))
+    val fuzz = LazyModule(new TLFuzzer(txns))
     xbar.node := TLDelayer(0.1)(fuzz.node)
     fuzz
   }
@@ -253,6 +253,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) e
   }
 }
 
-class TLMulticlientXbarTest(nManagers: Int, nClients: Int)(implicit p: Parameters) extends UnitTest(timeout = 5000000) {
+class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients)).module).io.finished
+  io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module).io.finished
 }

src/main/scala/unittest/Configs.scala

@@ -6,62 +6,74 @@ import Chisel._
 import config._
 import rocketchip.{BaseConfig, BasePlatformConfig}
 
+case object TestDurationMultiplier extends Field[Int]
+
+class WithTestDuration(x: Int) extends Config((site, here, up) => {
+  case TestDurationMultiplier => x
+})
+
 class WithUncoreUnitTests extends Config((site, here, up) => {
   case uncore.tilelink.TLId => "L1toL2"
   case UnitTests => (q: Parameters) => {
     implicit val p = q
+    val txns = 100 * site(TestDurationMultiplier)
+    val timeout = 50000 * site(TestDurationMultiplier)
     Seq(
-      Module(new uncore.tilelink2.TLFuzzRAMTest),
+      Module(new uncore.tilelink2.TLFuzzRAMTest(  txns=3*txns, timeout=timeout)),
-      Module(new uncore.ahb.AHBBridgeTest(true)),
+      Module(new uncore.ahb.AHBBridgeTest(true,   txns=8*txns, timeout=timeout)),
-      Module(new uncore.ahb.AHBNativeTest(true)),
+      Module(new uncore.ahb.AHBNativeTest(true,   txns=6*txns, timeout=timeout)),
-      Module(new uncore.ahb.AHBNativeTest(false)),
+      Module(new uncore.ahb.AHBNativeTest(false,  txns=6*txns, timeout=timeout)),
-      Module(new uncore.apb.APBBridgeTest(true)),
+      Module(new uncore.apb.APBBridgeTest(true,   txns=6*txns, timeout=timeout)),
-      Module(new uncore.apb.APBBridgeTest(false)),
+      Module(new uncore.apb.APBBridgeTest(false,  txns=6*txns, timeout=timeout)),
-      Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
+      Module(new uncore.axi4.AXI4LiteFuzzRAMTest( txns=6*txns, timeout=timeout)),
-      Module(new uncore.axi4.AXI4FullFuzzRAMTest),
+      Module(new uncore.axi4.AXI4FullFuzzRAMTest( txns=3*txns, timeout=timeout)),
-      Module(new uncore.axi4.AXI4BridgeTest)) }
+      Module(new uncore.axi4.AXI4BridgeTest(      txns=3*txns, timeout=timeout))) }
 })
 
-class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BasePlatformConfig)
-
 class WithTLSimpleUnitTests extends Config((site, here, up) => {
   case UnitTests => (q: Parameters) => {
     implicit val p = q
+    val txns = 100 * site(TestDurationMultiplier)
+    val timeout = 50000 * site(TestDurationMultiplier)
     Seq(
-      Module(new uncore.tilelink2.TLRAMSimpleTest(1)),
+      Module(new uncore.tilelink2.TLRAMSimpleTest(1,        txns=15*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMSimpleTest(4)),
+      Module(new uncore.tilelink2.TLRAMSimpleTest(4,        txns=15*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
+      Module(new uncore.tilelink2.TLRAMSimpleTest(16,       txns=15*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMZeroDelayTest(4)),
+      Module(new uncore.tilelink2.TLRAMZeroDelayTest(4,     txns=15*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRR0Test),
+      Module(new uncore.tilelink2.TLRR0Test(                txns= 3*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRR1Test),
+      Module(new uncore.tilelink2.TLRR1Test(                txns= 3*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMRationalCrossingTest),
+      Module(new uncore.tilelink2.TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMAsyncCrossingTest),
+      Module(new uncore.tilelink2.TLRAMAsyncCrossingTest(   txns= 5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMAtomicAutomataTest) ) }
+      Module(new uncore.tilelink2.TLRAMAtomicAutomataTest(  txns=10*txns, timeout=timeout)) ) }
 })
 
 class WithTLWidthUnitTests extends Config((site, here, up) => {
   case UnitTests => (q: Parameters) => {
     implicit val p = q
+    val txns = 100 * site(TestDurationMultiplier)
+    val timeout = 50000 * site(TestDurationMultiplier)
     Seq(
-      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)),
+      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMFragmenterTest(16,  64)),
+      Module(new uncore.tilelink2.TLRAMFragmenterTest(16,  64, txns=15*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4,  16)),
+      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4,  16, txns=15*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1,  1)),
+      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1,  1, txns= 1*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64)),
+      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64,  4)) ) }
+      Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64,  4, txns= 5*txns, timeout=timeout)) ) }
 })
 
 class WithTLXbarUnitTests extends Config((site, here, up) => {
   case UnitTests => (q: Parameters) => {
     implicit val p = q
+    val txns = 100 * site(TestDurationMultiplier)
+    val timeout = 50000 * site(TestDurationMultiplier)
     Seq(
-      Module(new uncore.tilelink2.TLRAMXbarTest(1)),
+      Module(new uncore.tilelink2.TLRAMXbarTest(1,           txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMXbarTest(2)),
+      Module(new uncore.tilelink2.TLRAMXbarTest(2,           txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMXbarTest(8)),
+      Module(new uncore.tilelink2.TLRAMXbarTest(8,           txns=5*txns, timeout=timeout)),
-      //Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4)),
+      Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)) ) }
-      Module(new uncore.tilelink2.TLMulticlientXbarTest(1,4)) ) }
 })
 
-class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new BasePlatformConfig)
+class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)
-class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new BasePlatformConfig)
+class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)
-class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new BasePlatformConfig)
+class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)
+class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)