riscv/rocket-chip
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update vector exception instructions

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This commit is contained in:
Yunsup Lee
2012-03-18 16:36:12 -07:00
parent 7493d55d3f
commit 98e10ddc3c
1 changed files with 7 additions and 7 deletions
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14
rocket/src/main/scala/instructions.scala
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@@ -249,14 +249,14 @@ object Instructions
val VSETVL = Bits("b?????_?????_000000000000_101_1110011",32); val VSETVL = Bits("b?????_?????_000000000000_101_1110011",32);
val VF = Bits("b00000_?????_????????????_111_1110011",32); val VF = Bits("b00000_?????_????????????_111_1110011",32);
// vector supervisor instructions // vector supervisor instructions
val VENQCMD = Bits("b00000_?????_?????_1000000000_1111011",32) val VENQCMD = Bits("b00000_?????_?????_1100000011_1111011",32)
val VENQIMM1 = Bits("b00000_?????_?????_1000000001_1111011",32) val VENQIMM1 = Bits("b00000_?????_?????_1100000100_1111011",32)
val VENQIMM2 = Bits("b00000_?????_?????_1000000010_1111011",32) val VENQIMM2 = Bits("b00000_?????_?????_1100000101_1111011",32)
val VENQCNT = Bits("b00000_?????_?????_1000000011_1111011",32) val VENQCNT = Bits("b00000_?????_?????_1100000110_1111011",32)
val VXCPTEVAC = Bits("b00000_?????_00000_1100000000_1111011",32) val VXCPTEVAC = Bits("b00000_?????_00000_1100000000_1111011",32)
val VXCPTKILL = Bits("b00000_00000_00000_1100000001_1111011",32) val VXCPTKILL = Bits("b00000_00000_00000_1000000010_1111011",32)
val VXCPTWAIT = Bits("b00000_00000_00000_1100000010_1111011",32) val VXCPTWAIT = Bits("b00000_00000_00000_1100000001_1111011",32)
val VXCPTHOLD = Bits("b00000_00000_00000_1100000011_1111011",32) val VXCPTHOLD = Bits("b00000_00000_00000_1100000010_1111011",32)
val NOP = ADDI & Bits("b00000000000000000000001111111111", 32); val NOP = ADDI & Bits("b00000000000000000000001111111111", 32);
} }