tilelink: remove obsolete addr_lo signal (#895)

When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.

src/main/scala/devices/tilelink/Error.scala

@@ -53,7 +53,6 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
     d.bits.size    := a.bits.size
     d.bits.source  := a.bits.source
     d.bits.sink    := UInt(0)
-    d.bits.addr_lo := a.bits.address
     d.bits.data    := UInt(0)
     d.bits.error   := a.bits.opcode =/= Hint // Hints may not error
 

src/main/scala/devices/tilelink/ROM.scala

@@ -42,7 +42,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
 
     val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
     val high = if (wrapSize == size) UInt(0) else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
-    in.d.bits := edge.AccessAck(in.a.bits, UInt(0), Mux(high.orR, UInt(0), rom(index)))
+    in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, UInt(0), rom(index)))
 
     // Tie off unused channels
     in.b.valid := Bool(false)

src/main/scala/devices/tilelink/TestRAM.scala

@@ -52,7 +52,7 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
     val legal = address.contains(in.a.bits.address)
     val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
 
-    in.d.bits := edge.AccessAck(in.a.bits, UInt(0), !legal)
+    in.d.bits := edge.AccessAck(in.a.bits, !legal)
     in.d.bits.data := Cat(mem(memAddress).reverse)
     in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
     when (in.a.fire() && hasData && legal) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) }

src/main/scala/devices/tilelink/Zero.scala

@@ -36,7 +36,7 @@ class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean
 
     a.ready := in.d.ready
     in.d.valid := a.valid
-    in.d.bits := edge.AccessAck(a.bits, UInt(0))
+    in.d.bits := edge.AccessAck(a.bits)
     in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
 
     // Tie off unused channels