riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port

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Colin Schmidt
2015-10-20 19:05:10 -07:00
parent 2cee8c8bec 1a1185be3f
commit 97f29b1618
6 changed files with 42 additions and 42 deletions
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rocket/src/main/scala/icache.scala
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@@ -7,7 +7,6 @@ import Util._
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLKey(p(TLId))).dataBeats
val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
val outerAddrBits = p(TLKey(p(TLId))).addrBits
val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats
}