riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port

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Colin Schmidt committed 2015-10-21 11:33:42 -07:00
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commit 97f29b1618
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rocket/src/main/scala/icache.scala
-1
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@@ -7,7 +7,6 @@ import Util._
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLKey(p(TLId))).dataBeats
val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
val outerAddrBits = p(TLKey(p(TLId))).addrBits
val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats
}