diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index cb9bb685..a6862b45 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -131,7 +131,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val reg_fflags = Reg(UInt(width = 5))
   val reg_frm = Reg(UInt(width = 3))
 
-  val irq_rocc = Bool(!p(BuildRoCC).isEmpty) && io.rocc.interrupt
+  val irq_rocc = Bool(usingRoCC) && io.rocc.interrupt
 
   io.interrupt_cause := 0
   io.interrupt := io.interrupt_cause(xLen-1)
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 7418af4f..76691620 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -7,7 +7,6 @@ import Util._
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
   val outerDataBeats = p(TLKey(p(TLId))).dataBeats
   val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
-  val outerAddrBits = p(TLKey(p(TLId))).addrBits
   val refillCyclesPerBeat = outerDataBits/rowBits
   val refillCycles = refillCyclesPerBeat*outerDataBeats
 }
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 19e898ec..f99f4979 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -718,7 +718,6 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   require(isPow2(nSets))
   require(isPow2(nWays)) // TODO: relax this
   require(rowBits <= outerDataBits)
-  require(paddrBits-blockOffBits == outerAddrBits)
   require(untagBits <= pgIdxBits)
 
   val wb = Module(new WritebackUnit)
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index 91397fcd..e1612361 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -6,7 +6,8 @@ import Chisel._
 import uncore._
 import Util._
 
-case object RoCCMaxTaggedMemXacts extends Field[Int]
+case object RoccMaxTaggedMemXacts extends Field[Int]
+case object RoccNMemChannels extends Field[Int]
 
 class RoCCInstruction extends Bundle
 {
@@ -41,7 +42,7 @@ class RoCCInterface(implicit p: Parameters) extends Bundle {
   
   // These should be handled differently, eventually
   val imem = new ClientUncachedTileLinkIO
-  val dmem = new ClientUncachedTileLinkIO
+  val dmem = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
   val iptw = new TLBPTWIO
   val dptw = new TLBPTWIO
   val pptw = new TLBPTWIO
@@ -122,8 +123,8 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
 
   io.imem.acquire.valid := false
   io.imem.grant.ready := false
-  io.dmem.acquire.valid := false
-  io.dmem.grant.ready := false
+  io.dmem.head.acquire.valid := false
+  io.dmem.head.grant.ready := false
   io.iptw.req.valid := false
   io.dptw.req.valid := false
   io.pptw.req.valid := false
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 2e9cb085..5da682a3 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -7,7 +7,7 @@ import junctions._
 import uncore._
 import Util._
 
-case object BuildFPU extends Field[Option[Parameters => FPU]]
+case object UseFPU extends Field[Boolean]
 case object FDivSqrt extends Field[Boolean]
 case object XLen extends Field[Int]
 case object FetchWidth extends Field[Int]
@@ -26,26 +26,26 @@ trait HasCoreParameters extends HasAddrMapParameters {
   implicit val p: Parameters
   val xLen = p(XLen)
 
+  val usingVM = p(UseVM)
+  val usingFPU = p(UseFPU)
+  val usingFDivSqrt = p(FDivSqrt)
+  val usingRoCC = !p(BuildRoCC).isEmpty
+  val usingFastMulDiv = p(FastMulDiv)
+  val fastLoadWord = p(FastLoadWord)
+  val fastLoadByte = p(FastLoadByte)
+
   val retireWidth = p(RetireWidth)
   val fetchWidth = p(FetchWidth)
   val coreInstBits = p(CoreInstBits)
   val coreInstBytes = coreInstBits/8
   val coreDataBits = xLen
   val coreDataBytes = coreDataBits/8
-  val coreDCacheReqTagBits = p(CoreDCacheReqTagBits)
+  val coreDCacheReqTagBits = 7 + (2 + (if(!usingRoCC) 0 else 1))
   val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
   val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
   val mmioBase = p(MMIOBase)
   val nCustomMrwCsrs = p(NCustomMRWCSRs)
 
-  val usingVM = p(UseVM)
-  val usingFPU = !p(BuildFPU).isEmpty
-  val usingFDivSqrt = p(FDivSqrt)
-  val usingRoCC = !p(BuildRoCC).isEmpty
-  val usingFastMulDiv = p(FastMulDiv)
-  val fastLoadWord = p(FastLoadWord)
-  val fastLoadByte = p(FastLoadByte)
-
   // Print out log of committed instructions and their writeback values.
   // Requires post-processing due to out-of-order writebacks.
   val enableCommitLog = false
@@ -486,7 +486,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(vaddrBits-1,0)).toUInt
   io.dmem.req.bits.tag := Cat(ex_waddr, ex_ctrl.fp)
   io.dmem.req.bits.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
-  require(p(CoreDCacheReqTagBits) >= 6)
+  require(coreDCacheReqTagBits >= 6)
   io.dmem.invalidate_lr := wb_xcpt
 
   io.rocc.cmd.valid := wb_rocc_val
@@ -496,7 +496,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   io.rocc.cmd.bits.rs1 := wb_reg_wdata
   io.rocc.cmd.bits.rs2 := wb_reg_rs2
 
-  if (!p(BuildFPU).isEmpty && !p(BuildRoCC).isEmpty) {
+  if (!usingFPU && !usingRoCC) {
     io.fpu.cp_req <> io.rocc.fpu_req
     io.fpu.cp_resp <> io.rocc.fpu_resp
   } else {
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index b3419866..ce29b18e 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -7,31 +7,33 @@ import uncore._
 import Util._
 
 case object CoreName extends Field[String]
-case object NDCachePorts extends Field[Int]
-case object NPTWPorts extends Field[Int]
 case object BuildRoCC extends Field[Option[Parameters => RoCC]]
 
 abstract class Tile(resetSignal: Bool = null)
                    (implicit p: Parameters) extends Module(_reset = resetSignal) {
+  val usingRocc = !p(BuildRoCC).isEmpty
+  val nDCachePorts = 2 + (if(!usingRocc) 0 else 1)
+  val nPTWPorts = 2 + (if(!usingRocc) 0 else 3)
+  val nCachedTileLinkPorts = 1
+  val nUncachedTileLinkPorts = 1 + (if(!usingRocc) 0 else p(RoccNMemChannels))
+  val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
   val io = new Bundle {
-    val cached = new ClientTileLinkIO
-    val uncached = new ClientUncachedTileLinkIO
+    val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
+    val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
     val host = new HtifIO
   }
 }
 
 class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(resetSignal)(p) {
-  //TODO
-  val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
-  val icache = Module(new Frontend()(p.alterPartial({
-                 case CacheName => "L1I"
-                 case CoreName => "Rocket" })))
-  val dcache = Module(new HellaCache()(dcacheParams))
-  val ptw = Module(new PTW(p(NPTWPorts))(dcacheParams))
   val core = Module(new Rocket()(p.alterPartial({ case CoreName => "Rocket" })))
+  val icache = Module(new Frontend()(p.alterPartial({
+    case CacheName => "L1I"
+    case CoreName => "Rocket" })))
+  val dcache = Module(new HellaCache()(dcacheParams))
+  val ptw = Module(new PTW(nPTWPorts)(dcacheParams))
 
   dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
-  val dcArb = Module(new HellaCacheArbiter(p(NDCachePorts))(dcacheParams))
+  val dcArb = Module(new HellaCacheArbiter(nDCachePorts)(dcacheParams))
   dcArb.io.requestor(0) <> ptw.io.mem
   dcArb.io.requestor(1) <> core.io.dmem
   dcache.io.cpu <> dcArb.io.mem
@@ -44,25 +46,24 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
   core.io.ptw <> ptw.io.dpath
 
   //If so specified, build an FPU module and wire it in
-  p(BuildFPU) foreach { fpu => core.io.fpu <> fpu(p).io }
+  if (p(UseFPU)) core.io.fpu <> Module(new FPU()(p)).io
 
-  // Connect the caches and ROCC to the outer memory system
-  io.cached <> dcache.io.mem
-  // If so specified, build an RoCC module and wire it in
-  // otherwise, just hookup the icache
+   // Connect the caches and ROCC to the outer memory system
+  io.cached.head <> dcache.io.mem
+  // If so specified, build an RoCC module and wire it to core + TileLink ports,
+  // otherwise just hookup the icache
   io.uncached <> p(BuildRoCC).map { buildItHere =>
     val rocc = buildItHere(p)
-    val memArb = Module(new ClientTileLinkIOArbiter(3))
+    val iMemArb = Module(new ClientTileLinkIOArbiter(2))
     val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
     core.io.rocc <> rocc.io
     dcIF.io.requestor <> rocc.io.mem
     dcArb.io.requestor(2) <> dcIF.io.cache
-    memArb.io.in(0) <> icache.io.mem
-    memArb.io.in(1) <> rocc.io.imem
-    memArb.io.in(2) <> rocc.io.dmem
+    iMemArb.io.in(0) <> icache.io.mem
+    iMemArb.io.in(1) <> rocc.io.imem
     ptw.io.requestor(2) <> rocc.io.iptw
     ptw.io.requestor(3) <> rocc.io.dptw
     ptw.io.requestor(4) <> rocc.io.pptw
-    memArb.io.out
-  }.getOrElse(icache.io.mem)
+    rocc.io.dmem :+ iMemArb.io.out
+  }.getOrElse(List(icache.io.mem))
 }