riscv/rocket-chip
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DM cache with assoc-aware subunits passes all asm and bmarks

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This commit is contained in:
Henry Cook
2012-01-18 17:53:26 -08:00
parent 8623d58724
commit 97f0852b17
2 changed files with 11 additions and 11 deletions
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7
rocket/src/main/scala/util.scala
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@ -42,11 +42,8 @@ object OHToUFix
{
def apply(in: Bits): UFix =
{
var out = UFix(0)
for(i <- 0 until in.getWidth)
if(in(i) == Bits(1))
out = UFix(i)
out
val out = MuxCase( UFix(0), (0 until in.getWidth).map( i => (in(i).toBool, UFix(i))))
out.toUFix
}
}