From 97f0852b17a15dc4fe00edce94ab1740d81460f0 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 18 Jan 2012 17:53:26 -0800 Subject: [PATCH] DM cache with assoc-aware subunits passes all asm and bmarks --- rocket/src/main/scala/nbdcache.scala | 15 +++++++++------ rocket/src/main/scala/util.scala | 7 ++----- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 9959089f..2d0d1229 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -725,10 +725,9 @@ class HellaCacheDM(lines: Int) extends Component { val wb = new WritebackUnit val wb_arb = (new Arbiter(2)) { new WritebackReq() } wb_arb.io.out <> wb.io.req - wb.io.data_req.bits.inner_req <> data_arb.io.in(3).bits - wb.io.data_req.ready <> data_arb.io.in(3).ready - wb.io.data_req.valid <> data_arb.io.in(3).valid - + wb.io.data_req.bits.inner_req <> data_arb.io.in(3).bits //TODO + wb.io.data_req.ready := data_arb.io.in(3).ready + data_arb.io.in(3).valid := wb.io.data_req.valid wb.io.data_resp <> data.io.resp // cpu tag check @@ -821,7 +820,9 @@ class HellaCacheDM(lines: Int) extends Component { mshr.io.mem_resp_val := io.mem.resp_val && (~rr_count === UFix(0)) mshr.io.mem_resp_tag := io.mem.resp_tag mshr.io.mem_req <> wb.io.refill_req - mshr.io.meta_req <> meta_arb.io.in(1) + mshr.io.meta_req.bits.inner_req <> meta_arb.io.in(1).bits //TODO + mshr.io.meta_req.ready := meta_arb.io.in(1).ready + meta_arb.io.in(1).valid := mshr.io.meta_req.valid mshr.io.replay <> replayer.io.replay replayer.io.sdq_enq.valid := tag_miss && r_req_write && (!dirty || wb_rdy) && mshr.io.req_rdy replayer.io.sdq_enq.bits := storegen.io.dout @@ -875,7 +876,9 @@ class HellaCacheDM(lines: Int) extends Component { flushed <== flushed && !r_cpu_req_val || r_cpu_req_val && r_req_flush && flush_rdy && flusher.io.req.ready flusher.io.req.valid := r_cpu_req_val && r_req_flush && flush_rdy && !flushed flusher.io.wb_req <> wb_arb.io.in(0) - flusher.io.meta_req <> meta_arb.io.in(0) + flusher.io.meta_req.bits.inner_req <> meta_arb.io.in(0).bits //TODO + flusher.io.meta_req.ready := meta_arb.io.in(0).ready + meta_arb.io.in(0).valid := flusher.io.meta_req.valid flusher.io.meta_resp <> meta.io.resp flusher.io.resp.ready := Bool(true) // we don't respond to flush requests diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 2e2dd20b..f9ddab80 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -42,11 +42,8 @@ object OHToUFix { def apply(in: Bits): UFix = { - var out = UFix(0) - for(i <- 0 until in.getWidth) - if(in(i) == Bits(1)) - out = UFix(i) - out + val out = MuxCase( UFix(0), (0 until in.getWidth).map( i => (in(i).toBool, UFix(i)))) + out.toUFix } }