riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

made I$ associative

Browse Source
This commit is contained in:
Andrew Waterman
2012-01-24 16:51:30 -08:00
parent aa3465699b
commit 97c379f1d7
3 changed files with 56 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
rocket/src/main/scala/util.scala
View File

@ -16,6 +16,11 @@ object log2up
def apply(in: Int) = if (in == 1) 1 else ceil(log(in)/log(2)).toInt
}
object ispow2
{
def apply(in: Int) = in > 0 && ((in & (in-1)) == 0)
}
object FillInterleaved
{
def apply(n: Int, in: Bits) =
@ -58,7 +63,7 @@ object UFixToOH
object LFSR16
{
def apply(increment: Bool) =
def apply(increment: Bool = Bool(true)) =
{
val width = 16
val lfsr = Reg(resetVal = UFix(1, width))