From 97c379f1d7a5df150d021162d1c239ec7a96baba Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 24 Jan 2012 16:51:30 -0800 Subject: [PATCH] made I$ associative --- rocket/src/main/scala/icache.scala | 80 ++++++++++++++++++------------ rocket/src/main/scala/top.scala | 2 +- rocket/src/main/scala/util.scala | 7 ++- 3 files changed, 56 insertions(+), 33 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index c0890738..a461be19 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -27,7 +27,7 @@ class ioIcache(view: List[String] = null) extends Bundle (view) val resp_val = Bool(OUTPUT); } -class ioICacheDM extends Bundle() +class ioICache extends Bundle() { val cpu = new ioImem(); val mem = new ioIcache().flip(); @@ -37,11 +37,12 @@ class ioICacheDM extends Bundle() // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines // parameters : // lines = # cache lines -class rocketICacheDM(lines: Int) extends Component { - val io = new ioICacheDM(); +class rocketICache(sets: Int, assoc: Int) extends Component { + val io = new ioICache(); + val lines = sets * assoc; val addrbits = PADDR_BITS; - val indexbits = log2up(lines); + val indexbits = log2up(sets); val offsetbits = OFFSET_BITS; val tagmsb = addrbits - 1; val taglsb = indexbits+offsetbits; @@ -54,15 +55,17 @@ class rocketICacheDM(lines: Int) extends Component { val rf_cnt_bits = log2up(REFILL_CYCLES); require(PGIDX_BITS >= taglsb); // virtually-indexed, physically-tagged constraint + require(ispow2(sets) && ispow2(assoc)); val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() }; val state = Reg(resetVal = s_reset); - val r_cpu_req_idx = Reg { Bits(width = PGIDX_BITS) } - val r_cpu_req_ppn = Reg { Bits(width = PPN_BITS) } + val r_cpu_req_idx = Reg { Bits() } + val r_cpu_req_ppn = Reg { Bits() } val r_cpu_req_val = Reg(resetVal = Bool(false)); val rdy = Wire() { Bool() } + val tag_hit = Wire() { Bool() } when (io.cpu.req_val && rdy) { r_cpu_req_val <== Bool(true) @@ -85,41 +88,56 @@ class rocketICacheDM(lines: Int) extends Component { when (io.mem.resp_val) { refill_count <== refill_count + UFix(1); } + + val repl_way = LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0) + val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix val tag_addr = Mux((state === s_refill_wait), r_cpu_req_idx(indexmsb,indexlsb), io.cpu.req_idx(indexmsb,indexlsb)).toUFix; val tag_we = (state === s_refill_wait) && io.mem.resp_val; - - val tag_array = Mem4(lines, r_cpu_miss_tag); - tag_array.setReadLatency(1); - tag_array.setTarget('inst); - val tag_rdata = tag_array.rw(tag_addr, r_cpu_miss_tag, tag_we); - - // valid bit array - val vb_array = Reg(resetVal = Bits(0, lines)); - when (io.cpu.invalidate) { - vb_array <== Bits(0,lines); - } - when (tag_we) { - vb_array <== vb_array.bitSet(r_cpu_req_idx(indexmsb,indexlsb).toUFix, UFix(1,1)); - } - - val tag_valid = vb_array(r_cpu_req_idx(indexmsb,indexlsb)).toBool; - val tag_hit = tag_valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb)) - - // data array val data_addr = Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(indexmsb,offsetbits), refill_count), io.cpu.req_idx(indexmsb, offsetbits-rf_cnt_bits)).toUFix; - val data_array = Mem4(lines*REFILL_CYCLES, io.mem.resp_data); - data_array.setReadLatency(1); - data_array.setTarget('inst); - val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val); + + val data_mux = new Mux1H(assoc, MEM_DATA_BITS) + var any_hit = Bool(false) + for (i <- 0 until assoc) + { + val repl_me = (repl_way === UFix(i)) + val tag_array = Mem4(lines, r_cpu_miss_tag); + tag_array.setReadLatency(1); + tag_array.setTarget('inst); + val tag_rdata = tag_array.rw(tag_addr, r_cpu_miss_tag, tag_we && repl_me); + + // valid bit array + val vb_array = Reg(resetVal = Bits(0, lines)); + when (io.cpu.invalidate) { + vb_array <== Bits(0,lines); + } + when (tag_we && repl_me) { + vb_array <== vb_array.bitSet(r_cpu_req_idx(indexmsb,indexlsb).toUFix, UFix(1,1)); + } + + val valid = vb_array(r_cpu_req_idx(indexmsb,indexlsb)).toBool; + val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb)) + + // data array + val data_array = Mem4(lines*REFILL_CYCLES, io.mem.resp_data); + data_array.setReadLatency(1); + data_array.setTarget('inst); + val data_out = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val && repl_me) + + data_mux.io.sel(i) := hit + data_mux.io.in(i) := (data_out >> word_shift)(databits-1,0); + + any_hit = any_hit || hit + } + tag_hit := any_hit // output signals io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_hit; - rdy <== !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit); - io.cpu.resp_data := data_array_rdata >> Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix + rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit); + io.cpu.resp_data := data_mux.io.out io.mem.req_val := (state === s_request); io.mem.req_addr := r_cpu_miss_addr(tagmsb,indexlsb).toUFix diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index daa049be..b38c9ddf 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -15,7 +15,7 @@ class Top() extends Component { val io = new ioTop(); val cpu = new rocketProc(); - val icache = new rocketICacheDM(128); // # 64 byte cache lines + val icache = new rocketICache(128, 2); // 128 sets x 2 ways val icache_pf = new rocketIPrefetcher(); val dcache = new HellaCacheDM(128); val arbiter = new rocketMemArbiter(); diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 04ef0382..cf2d05d8 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -16,6 +16,11 @@ object log2up def apply(in: Int) = if (in == 1) 1 else ceil(log(in)/log(2)).toInt } +object ispow2 +{ + def apply(in: Int) = in > 0 && ((in & (in-1)) == 0) +} + object FillInterleaved { def apply(n: Int, in: Bits) = @@ -58,7 +63,7 @@ object UFixToOH object LFSR16 { - def apply(increment: Bool) = + def apply(increment: Bool = Bool(true)) = { val width = 16 val lfsr = Reg(resetVal = UFix(1, width))