refactor unittest framework
as a result, there's another SUITE that needs to run
This commit is contained in:
parent
ae026edeb3
commit
97809b183f
@ -35,6 +35,7 @@ env:
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matrix:
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- SUITE=RocketSuite
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- SUITE=GroundtestSuite
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- SUITE=UnittestSuite
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# blacklist private branches
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branches:
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4
Makefrag
4
Makefrag
@ -4,8 +4,8 @@ $(error Please set environment variable RISCV. Please take a look at README)
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endif
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MODEL ?= TestHarness
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PROJECT := rocketchip
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CFG_PROJECT := $(PROJECT)
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PROJECT ?= rocketchip
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CFG_PROJECT ?= $(PROJECT)
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CXX ?= g++
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CXXFLAGS := -O1
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@ -39,14 +39,20 @@ $(error Set SUITE to the regression suite you want to run)
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endif
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ifeq ($(SUITE),RocketSuite)
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PROJECT=rocketchip
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CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig
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endif
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ifeq ($(SUITE),GroundtestSuite)
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PROJECT=rocketchip
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CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
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BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
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ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig \
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UnitTestConfig
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ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig
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endif
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ifeq ($(SUITE),UnittestSuite)
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PROJECT=rocketchip.utest
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CONFIGS=UnitTestConfig
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endif
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ifeq ($(SUITE), JtagDtmSuite)
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@ -117,65 +123,65 @@ $(RISCV)/install.stamp:
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# Builds the various simulators
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stamps/%/emulator-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
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date > $@
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stamps/%/emulator-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV))
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
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date > $@
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stamps/%/emulator-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) debug
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
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date > $@
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stamps/%/vsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
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date > $@
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stamps/%/vsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV))
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
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date > $@
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stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) debug
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+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
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date > $@
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# Runs tests on one of the simulators
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stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
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date > $@
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stamps/%/emulator-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
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date > $@
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stamps/%/emulator-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
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$(MAKE) -C $(abspath $(TOP))/emulator CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
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$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
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date > $@
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stamps/%/vsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
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date > $@
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stamps/%/vsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
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date > $@
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stamps/%/vsim-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
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mkdir -p $(dir $@)
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$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
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$(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
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$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
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date > $@
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# The torture tests run subtly differently on the different targets, so they
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@ -1,26 +0,0 @@
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package coreplex
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import Chisel._
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import unittest.UnitTestSuite
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import rocket.Tile
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import uncore.tilelink.TLId
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import cde.Parameters
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class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
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require(tc.nSlaves == 0)
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require(tc.nMemChannels == 0)
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io.master.mmio.foreach { port =>
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port.acquire.valid := Bool(false)
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port.grant.ready := Bool(false)
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}
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io.debug.req.ready := Bool(false)
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io.debug.resp.valid := Bool(false)
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val l1params = p.alterPartial({ case TLId => "L1toL2" })
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val tests = Module(new UnitTestSuite()(l1params))
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override def hasSuccessFlag = true
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io.success.get := tests.io.finished
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}
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@ -7,7 +7,6 @@ import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices.NTiles
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import unittest._
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import junctions._
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import scala.collection.mutable.LinkedHashSet
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import scala.collection.immutable.HashMap
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@ -16,29 +15,6 @@ import scala.math.max
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import coreplex._
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import ConfigUtils._
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class WithUnitTest extends Config(
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(pname, site, here) => pname match {
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case BuildCoreplex => {
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val groundtest = if (site(XLen) == 64)
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DefaultTestSuites.groundtest64
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else
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DefaultTestSuites.groundtest32
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TestGeneration.addSuite(groundtest("p"))
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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(p: Parameters, c: CoreplexConfig) => Module(new UnitTestCoreplex(p, c))
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}
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case UnitTests => (testParams: Parameters) =>
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JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 0)
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case FPUKey => None
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case UseAtomics => false
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case UseCompressed => false
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case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
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case _ => throw new CDEMatchError
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})
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class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
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class WithGroundTest extends Config(
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(pname, site, here) => pname match {
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case BuildCoreplex =>
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46
src/main/scala/rocketchip/UnitTest.scala
Normal file
46
src/main/scala/rocketchip/UnitTest.scala
Normal file
@ -0,0 +1,46 @@
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// See LICENSE for license details.
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package rocketchip.utest
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import scala.collection.mutable.LinkedHashSet
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import Chisel._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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import util.{ParameterizedBundle}
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import rocket._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule, LazyModuleImp}
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import coreplex._
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import rocketchip._
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import unittest._
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class WithUnitTest extends Config(
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(pname, site, here) => pname match {
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case UnitTests => (testParams: Parameters) => {
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val groundtest = if (site(XLen) == 64)
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DefaultTestSuites.groundtest64
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else
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DefaultTestSuites.groundtest32
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TestGeneration.addSuite(groundtest("p"))
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TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
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JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
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}
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case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
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case _ => throw new CDEMatchError
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})
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class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
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class TestHarness(implicit val p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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p(NCoreplexExtClients).assign(0)
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p(ConfigString).assign("")
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val l1params = p.alterPartial({ case TLId => "L1toL2" })
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val tests = Module(new UnitTestSuite()(l1params))
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io.success := tests.io.finished
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}
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