riscv/rocket-chip
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state machine bug on uncached write hits

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This commit is contained in:
Henry Cook 2015-01-05 19:48:49 -08:00
parent f58f8bf385
commit 973eb43128
1 changed files with 3 additions and 1 deletions
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4
uncore/src/main/scala/cache.scala
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@ -870,7 +870,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
xact_data(local_data_resp_cnt) := mergeData(xact, xact_data(local_data_resp_cnt), xact_data(local_data_resp_cnt) := mergeData(xact, xact_data(local_data_resp_cnt),
io.data.resp.bits.data) io.data.resp.bits.data)
} }
when(local_data_resp_done) { state := s_meta_write } when(local_data_resp_done) {
state := Mux(co.messageHasData(xact), s_data_write, s_meta_write)
}
} }
is(s_data_write) { is(s_data_write) {
io.data.write.valid := Bool(true) io.data.write.valid := Bool(true)